July 5, 2011
22
USB to JTAG, SWD, Headers, and Power
1
1
2
2
3
3
4
4
5
5
6
6
D
D
C
C
B
B
A
A
Document Number:
Rev
Sheet
Date:
of
6/17/2011
1
2
C
Designer:
Drawn by:
Approved:
Drawing Title:
Page Title:
Size
Arnaldo Cruz
Arnaldo Cruz
*
0001
EK-LM3S9B90 and EK-LM3S9D90 Evaluation Board
Tempest, Reset, Test Pads
B
108 Wild Basin Rd.
Suite 350
Austin, TX 78746
TI AEC - Austin
C18
18pF
C17
18pF
C16
18pF
C15
18pF
RSTn
OSCin
OSCout
XTALN
XTALP
R8
12.4K
R7
9.1k
USBDP
USBDM
3.3V
C22
1uF
C19
0.1uF
C7
0.1uF
C8
0.1uF
C9
0.1uF
C10
0.1uF
C11
0.1uF
C6
1uF
C13
0.1uF
C20
0.1uF
C23
0.1uF
XOSC0
XOSC1
R9
1M
C5
18pF
C4
18pF
Y3
4.194304 MHz
ETH_TXOP
ETH_TXON
ETH_MDIO
ETH_LED0
ETH_LED1
ETH_RXIP
ETH_RXIN
USBPWR
USBFLT
USBID
3.3V
TMS
TCK
TDO
TDI
C1
0.1uF
VBUS
PF4
PB4
PB5
PB6
PB7
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PF0
PF1
PB2
PB3
PH0
PH1
PH2
PH5
PH6
PH7
PJ0
PJ1
PJ2
WAKEn
PG0
PG1
PE1
PE2
PE3
PE4
PE5
PE6
PE7
PC4
PC5
PC6
PC7
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PG7
3.3V
R6
10K
C2
0.1uF
R4
10K
PC0
PC1
PC2
PC3
R3
10K
R2
10K
R1
10K
PB2
PB3
PB4
PB5
PB6
PB7
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PF0
PF1
PF2
PF3
PF4
PF5
PH0
PH1
PH2
PH5
PH6
PH7
PE0
PE1
PE2
PE3
PE4
PE5
PE6
PE7
PG0
PG1
PG7
1
4
2
3
RESET
SW1
PJ0
PJ1
PJ2
PE0
PF5
VBAT
RSTn
3.3V
R5
10K
HIBn
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PC4
PC5
PC6
PC7
WAKEn
VBAT
HIBn
LM3S9B90/LM3S9D90
PA0/U0RX
26
PA1/U0TX
27
PA2/SSI0CLK
28
PA3/SSI0FSS
29
PA4/SSI0RX
30
PA5/SSI0TX
31
PC0/TCK/SWCLK
80
PC1/TMS/SWDIO
79
PC2/TDI
78
PC3/TDO/SWO
77
PC4
25
PC5
24
PC6
23
PC7
22
PD0
10
PD1
11
PD2
12
PD3
13
PD4
97
PD5
98
PD6
99
PD7
100
GND
9
GND
21
ERBIAS
33
RST
64
LDO
7
OSC0
48
OSC1
49
PB0/USB0ID
66
PB1/USB0VBUS
67
PB2/I2C0SCL
72
PB3/I2C0SDA
65
PB4
92
PB5
91
PB6
90
PB7
89
PE0
74
PE1
75
PE2
95
PE3
96
PE4
6
PE5
5
PA6
34
PA7
35
PE6
2
PE7
1
PF0
47
PF1
61
PF2/LED1
60
PF3/LED0
59
MDIO
58
TXON
46
TXOP
43
PF4
42
PG0
19
PG1
18
XTALNPHY
17
XTALPPHY
16
PF5
41
RXIP
40
RXIN
37
PG7
36
PH0
86
PH1
85
PH2
84
PH3/USB0EPEN
83
AVDD
3
AGND
4
VDD33
8
VDD33
20
VDD33
32
VDD33
44
VDD33
56
VDD33
68
VDD33
81
VDD33
93
GND
45
GND
57
GND
69
GND
82
GND
94
CVDD
38
CVDD
88
HIB
51
PH4/USB0PFLT
76
USB0DP
71
USB0DM
70
USB0RBIAS
73
PH5
63
PH6
62
PH7
15
PJ0
14
PJ1
87
PJ2
39
WAKEn
50
XOSC0
52
XOSC1
53
GND
54
VBAT
55
U1
5V
1
2
Y1
16.000 MHz
C12
0.1uF
C14
0.1uF
SHDNn
VBUS
3.3V
R24
10K
1
2
Y2
25.000 MHz
JTAG/SWD
1
3
5
7
9
2
4
6
8
10
J1
HDR 2X5-MH-SHRD
VCP_RX
5V
PWR/UART
1
3
5
7
2
4
6
8
J2
HDR 2X4-MH-SHRD
DBG1
DBG2
TP1
TP2
TP3
TP4
TP5
TP6
TP7
TP8
TP9
TP10
TP11
TP12
TP13
TP14
TP15
TP16
TP17
TP18
TP19
TP20
TP21
TP22
TP23
TP24
TP25
TP26
TP27
TP28
TP29
TP30
TP31
TP32
TP33
TP34
TP35
TP36
TP37
TP38
TP39
TP40
TP41
TP42
TP43
TP44
TP45
TP46
TP47
TP48
TP49
TP50
TP51
TP52
TP53
TP54
TP55
TP56
TP57
TP58
TP59
TP60
TP61
TP62
TP63
TP64
TP65
TP66
TP67
TP68
FB1
120ohm @ 10
0 M
H
z
PA0
PA1
VCP_RX
VCP_TX
PB4
PD0
USR_PBn
USR_LED
JR1
JR2
JR3
JR4
VCP_TX
JR5
JR6
PF2
PF3
PF2
PF3
C3
0.1uF
3.3V
Revision History
Revision
A
2/24/2009
First release for prototypes.
Date
Description
B
4/15/2009
Released to production.
R23
10
CVDD
5VR
C
1/21/2010
DC regulators U2 and U4 replaced for TI parts.
6/17/2011
Add option to install either LM3S9B90 or LM3S9D90
1
1
2
2
3
3
4
4
5
5
6
6
D
D
C
C
B
B
A
A
Document Number:
Rev
Sheet
Date:
of
5/18/2009
1
2
B
Designer:
Drawn by:
Approved:
Drawing Title:
Page Title:
Size
Arnaldo Cruz
Arnaldo Cruz
*
0001
In Circuit Debug Interface (ICDI) Board
USB to JTAG, SWD
B
108 Wild Basin Rd.
Suite 350
Austin, TX 78746
Texas Instruments
1
2
Y1
6.000MHz
3.3V
3.3V
5V
5V
R5
27
R7
1.50k
R9
2.21k
USBP
USBM
5V
VCP_RX
VCP_TX_SWO
R13
330
VCP_RX
5V
5V
3.3V
C12
4.7uF
C11
4.7uF
5V
VIN
4
VOUT
5
SHDN
3
GND
2
NR
1
U3
PQ1LA333MSPQ
C7
18pF
C8
18pF
PWR/UART
1
3
5
7
2
4
6
8
J2
HDR 2X4-MH-SHRD
R15
330
PWR
D1
GREEN_LED
FB1
120ohm @ 100 MHz
5V
D-
D+
ID
G
1
2
3
4
G2
5
G1
G3
G4
J4 USB_MINI_B_RECEPTACLE
XTI
XTO
UDM
UDP
EECS
EESK
EEDATA
FT_SK
FT_DO
FT_DI
FT_CS
DBGENn
DBGMOD
VCP_TX_SWO
SWO_EN
TCK
TDI
TDO_SWO
TMS_SWDIO
VCP_TX
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
JTAG/SWD
J3
2X10 HDR-SHRD
JTAG/SWD
1
3
5
7
9
2
4
6
8
10
J1
HDR 2X5-MH-SHRD
TCK
TMS
TDI
TDO
SRSTn
3.3V
DBG1
DBG1
DBG2
1
4
2
3
RESET
SW1
12
11
13
U5D
SN74LVC125A
DBGRSTn
SRSTn
VSENSE
R12
475
CS
1
SK
2
DI
3
DO
4
GND
5
NC
7
ORG
6
VCC
8
1K 64X16
U2
CAT93C46
FB2
120ohm @ 100 MHz
VBUS
DBG2
DEBUG ACTIVE
D2
GREEN_LED
R1
10K
R2
10K
R3
10K
R4
10K
R11
10K
R8
10K
R10
10K
R14
10K
R6
27
C1
0.1uF
C9
0.1uF
C2
0.1uF
C3
0.1uF
C4
0.1uF
C5
0.1uF
C6
0.1uF
C13
0.1uF
GND
18
GND
25
GND
34
ADBUS0
24
ADBUS1
23
ADBUS2
22
ADBUS3
21
ADBUS4
20
ADBUS5
19
ADBUS6
17
ADBUS7
16
ACBUS0
15
ACBUS1
13
ACBUS2
12
ACBUS3
11
BDBUS0
40
BDBUS1
39
BDBUS2
38
BDBUS3
37
BDBUS4
36
BDBUS5
35
BDBUS6
33
BDBUS7
32
BCBUS0
30
BCBUS1
29
BCBUS2
28
BCBUS3
27
SI/WUA
10
SI/WUB
26
GND
9
AGND
45
VCC
3
VCC
42
VCCIOA
14
VCCIOB
31
AVCC
46
PWREN#
41
XTOUT
44
XTIN
43
EECS
48
EESK
1
EEDATA
2
TEST
47
RESET#
4
RSTOUT#
5
3V3OUT
6
USBDM
8
USBDP
7
U1
FT2232
Revision History
Revision
A
2/24/2009
First release for prototypes.
Date
Description
B
4/03/2009
Released for production.
R19
10
Содержание Stellaris LM3S9D90
Страница 5: ...July 5 2011 5 List of Tables Table C 1 EK LM3S9D90 Evaluation Board GPIO Usage 29 ...
Страница 6: ...6 July 5 2011 ...
Страница 10: ...Stellaris LM3S9D90 Evaluation Kit Overview 10 July 5 2011 ...
Страница 24: ...24 July 5 2011 ...
Страница 28: ...References 28 July 5 2011 ...
Страница 30: ...30 July 5 2011 ...