Texas Instruments PCM4222EVM, Руководство пользователя

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2.7.4 Digital High-Pass Filter
2.7.5 Overflow Output Indicators
2.7.6 AES3 Transmitter Operation
Hardware Configuration
The PCM4222 includes digital high-pass filtering that removes the dc component from the output signal.
The right and left channel filters can be enabled and disabled individually, using the HPFDR (pin 17) and
HPFDL (pin 18) inputs, respectively. These inputs are controlled via the HPFDR and HPFDL elements on
switch SW1.
Table 13 summarizes the operation for these switches.
Table 13. Digital High-Pass Filter Switch Operation
Switch SW1, HPFDR or HPFDL Digital High-Pass Filter Function
LO Enabled
HI Disabled
The PCM4222 includes two active-high overflow indicators, one each for the left and right channels. The
overflow indicators are provided at the OVFL (pin 37) and OVFR (pin 38) outputs. These outputs are
buffered by U17 and U18. The buffers drive light emitting diodes LED1 and LED2 on the EVM, providing
visual overflow indication for the left and right channels, respectively.
The EVM includes two Texas Instruments DIT4192 digital audio interface transmitters, U13 and U14. The
transmitters accept either Left Justified or I
2
S formatted PCM output data from the PCM4222 and then
encode it into an AES3 data stream, which is output at connectors J7 through J10. A tri-state buffer (U11)
is used to enable/disable the clock and data flow from the PCM4222 to the DIT4192 devices. The DIT
switch on SW3 is used to enable or disable the buffer.
Table 14 summarizes the DIT switch settings.
Table 14. DIT4192 Serial Data and Clock Enable Operation
Switch SW3, DIT DIT4192 Input Data/Clock Enable
LO Enabled. Data and clocks flow from the PCM4222 to U13 and U14.
Disabled. The tri-state buffer outputs are high impedance, with no
HI
clocks or data supplied to U13 and U14.
The DIT4192 includes an on-chip master clock divider, which is used to generate the output frame rate
clock for the AES3-encoded data. For PCM data, the output frame rate is normally the same as the
PCM4222 output sampling rate. The exception is for Single-Channel, Double Sampling Frequency
transmission, when the DIT4192 Mono mode operation is invoked (this topic is discussed later in this
section).
The DITCLK0 and DITCLK1 elements on switch SW3 determine the master clock divider settings for the
transmitters.
Table 15 summarizes the operation for the DITCLK0 and DITCLK1 switches, and indicates
the selections corresponding to the three sampling modes for the PCM4222.
Table 15. DIT4192 Master Clock Divider Configuration
Switch SW3, DITCLK1 Switch SW3, DITCLK0 DIT4192 Master Clock Divider
LO LO Divide by 128 (PCM4222 Quad Speed mode)
LO HI Divide by 256 (PCM4222 Dual Speed mode)
HI LO Divide by 384 (Not Used)
HI HI Divide by 512 (PCM4222 Normal mode)
SBAU124 – December 2006 PCM4222EVM User's Guide 13
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