Texas Instruments PanelBus TFP503 Скачать руководство пользователя страница 2

Страница: 2 / 27

PanelBus



SLDS149 − AUGUST 2004

POST OFFICE BOX 655303

•

DALLAS, TEXAS 75265

76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100

50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26

TQFP PACKAGE

(TOP VIEW)

QO1
QO0
HSYNC
VSYNC
DE
OGND
ODCK
OV

RSVD
CTL2
CTL1
DGND
DV

QE23
QE22
QE21
QE20
QE19
QE18
QE17
QE16
OV

OGND
QE15
QE14

OGND

QO23

AGND

Rx2+

Rx2−

Rx1+

Rx1−

Rx0+

Rx0−

RxC+

RxC−

DDC_SCL

DDC_SDA

DDC_SA

RCL

RDA

PGND

OCK_INV

QO22

QO21

QO20

QO19

QO18

QO17

QO16

DGND

CAP

QO15

QO14

QO13

QO12

QO1

QO10

QO9

QO8

OGND

QO7

QO6

QO5

QO4

QO3

QO2

DFO

PIXS

DGND

SCDT

PDO

QE0

QE1

QE2

QE3

QE4

QE5

QE6

QE7

OGND

QE8

QE9

QE10

QE1

QE12

QE13

Содержание PanelBus TFP503

Страница 1: ...ock supports TFT or DSTN panels and provides an option for time staggered pixel outputs for reduced ground bounce PowerPAD advanced packaging technology results in best of class power dissipation footprint and ultra low ground inductance The TFP503 combines PanelBus circuit innovation and unique implementation for HDCP key protection with TI s advanced 0 18 µm EPIC 5 CMOS process technology to ach...

Страница 2: ... 14 13 12 11 10 9 8 7 6 5 4 3 2 1 TQFP PACKAGE TOP VIEW QO1 QO0 HSYNC VSYNC DE OGND ODCK OVDD RSVD CTL2 CTL1 DGND DVDD QE23 QE22 QE21 QE20 QE19 QE18 QE17 QE16 OVDD OGND QE15 QE14 OGND QO23 OVDD AGND Rx2 Rx2 AVDD Rx1 Rx1 AVDD Rx0 Rx0 AVDD RxC RxC AVDD DDC_SCL DDC_SDA DDC_SA RCL RDA PVDD1 PGND PVDD2 OCK_INV QO22 QO21 QO20 QO19 QO18 QO17 QO16 DGND CAP QO15 QO14 QO13 QO12 QO11 QO10 QO9 QO8 OGND OV DD ...

Страница 3: ...2 GRN 7 0 CTL1 BLU 7 0 VSYNC HSYNC QE 23 0 QO 23 0 ODCK DE SCDT CTL2 CTL1 VSYNC HSYNC 1 8 V Regulator 3 3 V Internal 50 Ω Termination Rx2 Rx2 Rx1 Rx1 Rx0 Rx0 RxC RxC HDCP Decryption RED 7 0 CTL2 GRN 7 0 CTL1 BLU 7 0 VSYNC HSYNC Panel Interface Encrypted Embedded HDCP Keys RCL 3 3 V RDA Key Decryption RAM Block I2C Slave I F for DDC DDC_SCL DDC_SA DDC_SDA I2C Control Registers Data Recovery and Syn...

Страница 4: ...he ODCK only clocks when DE is high otherwise ODCK is held low when DE is low High DSTN support ODCK held low when DE is low Low TFT support ODCK runs continuously DGND 5 39 68 Digital ground Ground reference and current return for digital core DVDD 6 38 Digital VDD Power supply for digital core Nominally 3 3 V HSYNC 48 O Horizontal sync output OCK_INV 100 I ODCK polarity Selects the ODCK edge on ...

Страница 5: ...held low when in 1 pixel clock mode Output data is synchronized to the output data clock ODCK LSB QO0 terminal 49 MSB QO7 terminal 56 QO 8 15 59 66 O Odd green pixel output Output for only odd green pixels when in 2 pixel clock mode Not used and held low when in 1 pixel clock mode Output data is synchronized to the output data clock ODCK LSB QO8 terminal 59 MSB QO15 terminal 66 QO 16 23 69 75 77 O...

Страница 6: ...Vertical sync output absolute maximum ratings over operating free air temperature unless otherwise noted Supply voltage range DVDD AVDD OVDD PVDD 0 3 V to 4 V Input voltage logic analog signals 0 3 V to 4 V Operating ambient temperature range 0 C to 70 C Storage temperature range 65 C to 150 C Case temperature for 10 seconds 260 C Lead temperature 1 6 mm 1 16 inch from case for 10 seconds 260 C ES...

Страница 7: ... 10 13 19 mA IOL D Low level output drive current see Note 4 ST Low VOL 0 4 V 5 7 11 mA IIH High level digital input current see Note 3 VIH DVDD 20 µA IIL Low level digital input current see Note 3 VIL 0 0 V 60 µA IOZ Hi Z output leakage current PD Low or PDO Low 20 µA NOTES 3 Digital inputs are labeled I in I O column of the Terminal Functions Table 4 Digital outputs are labeled O in I O column o...

Страница 8: ... 1 pixel clock PIXS Low ST Low CL 10 pF 1 2 ns OCK_INV Low ST High CL 10 pF 1 2 ns tsu 1 Setup time data and control signals to falling 2 pixel clock PIXS High ST Low CL 10 pF 2 7 ns tsu 1 Setup time data and control signals to falling edge of ODCK see Note 11 STAG High OCK_INV Low ST High CL 10 pF 2 7 ns 2 pixel STAG PIXS High ST Low CL 10 pF 1 7 ns STAG Low OCK_INV Low ST High CL 10 pF 1 7 ns 1 ...

Страница 9: ... th 2 Hold time data and control signals to rising edge of ODCK see Note 11 2 pixel STAG PIXS High ST Low CL 10 pF 1 4 ns STAG Low OCK_INV High ST High CL 10 pF 1 4 ns f ODCK ODCK frequency PIXS Low 25 165 MHz f ODCK ODCK frequency PIXS High 12 5 82 5 MHz ODCK duty cycle 40 50 60 td PDL Delay from PD low to Hi Z outputs 18 ns td PDOL Delay from PDO low to Hi Z outputs 18 ns t HSC Time between DE t...

Страница 10: ...h 2 VOH VOL VOH VOL VOH VOL VOH VOL VOH VOL VOH VOL ODCK QE 23 0 QO 23 0 DE CTL 2 1 HSYNC VSYNC OCK_INV Figure 4 Data Setup and Hold Time to Rising and Falling Edge of ODCK Figure 5 ODCK High to QE 23 0 Staggered Data Output Figure 6 Analog Input Intra Pair Differential Skew 50 VOH td st ODCK QE 23 0 50 tsk D Tx Tx Figure 7 Delay From PD Low to Hi Z Outputs Figure 8 Delay From PDO Low to Hi Z Outp...

Страница 11: ... 9 Delay From PD Low to High Before Inputs Are Active Figure 10 Minimum Time PD Low PD DFO ST PIXS STAG Rx 2 0 Rx 2 0 OCK_INV VIH td PDLA td PDLM PD VIL tsk CC 50 50 TX2 TX1 TX0 Figure 11 Analog Input Channel to Channel Skew t HSC t FSC DE SCDT Figure 12 Time Between DE Transitions to SCDT Low and SCDT High ...

Страница 12: ...ting the need both for an external storage device to store the HDCP keys and for the customer to purchase HDCP keys from the licensing authority An encryption scheme ensures that the embedded HDCP keys are encrypted thus providing highest level of key security T M D S pixel data and control signal encoding Only one of two possible T M D S characters for a given pixel is transmitted at a given time...

Страница 13: ...e Channel 2 Channel 0 Channel C HDCP Encrypted TMDS Link Encrypted Keys B Keys and KSV I2C I2C Channel 1 EDID PROM Control and Authentication and Key Exchange KSV Key Selection Vector DE Pixel Data Clock Output Stream T M D S Decode HDPC Decrypt HDCP Encrypt T M D S Encode Figure 13 TI s HDCP Implementation for PC and Display System TFP503 clocking and data synchronization The TFP503 receives a cl...

Страница 14: ...AVDD The TFP503 is internally optimized using a laser trim process to precisely fix the single ended termination impedance at 50 Ω This fixed impedance eliminates the need for external termination resistors while providing optimum impedance matching to standard DVI cables having a characteristic impedance of 100 Ω Figure 14 shows a conceptual schematic of a TFP510 or TFP513 transmitter and TFP503 ...

Страница 15: ...er down output drive mode if left unconnected Drive strength ST high for high drive strength ST low for low drive strength The TFP503 allows for selectable output drive strength on the data control and ODCK outputs See the dc specifications table for the values of IOH D and IOL D current drives for a given ST state The high output strength offers approximately two times the drive as the low output...

Страница 16: ... down when the link is considered inactive The SCDT can also be tied directly to the TFP503 PDO input to power down the output drivers when the link is inactive It is not recommended to use the SCDT to drive the PD input since once in complete power down the analog inputs are ignored and the SCDT state does not change An external system power management circuit to drive PD is preferred HDCP regist...

Страница 17: ...st errors in the I2C transmission by re reading this value when unexpected values are received This value is available at all times between updates AKSV Subaddress 10 Read Write Default 00 7 6 5 4 3 2 1 0 AKSV 7 0 Subaddress 11 Read Write Default 00 7 6 5 4 3 2 1 0 AKSV 15 8 Subaddress 12 Read Write Default 00 7 6 5 4 3 2 1 0 AKSV 23 16 Subaddress 13 Read Write Default 00 7 6 5 4 3 2 1 0 AKSV 31 2...

Страница 18: ...is written Bcaps Subaddress 40 Read Only Default 10 7 6 5 4 3 2 1 0 Rsvd Repeater KSV FIFO Fast Rsvd Rsvd Rsvd Rsvd Bit 6 REPEATER Video repeater capability This device is not a repeater Read as 0 Bit 5 READY KSV FIFO ready This device does not support repeater capability Read as 0 Bit 4 FAST This device supports 400 kHz transfers Read as 1 Bstatus Subaddress 41 Read Only Default 00 7 6 5 4 3 2 1 ...

Страница 19: ...s the 16 bit device ID for the TFP503 DEV_ID 15 0 is hardwired to 0x0501 REV_ID Subaddress C4 Read Only Default 01 7 6 5 4 3 2 1 0 REV_ID 7 0 This read only register contains the 8 bit revision ID for the TFP503 REV_ID 7 0 is hardwired to 0x01 I2C interface The I2C interface accesses the internal TFP503 registers This two terminal interface consists of one clock line DDC_SCL and one serial data li...

Страница 20: ...as shown in Figure 18 The subaddress is autoincremented after each data cycle The transmitting device must not drive the DDC_SDA signal during the acknowledge cycle so that the receiving device may drive the DDC_SDA signal low The not acknowledge A condition is indicated by the master by keeping the DDC_SDA signal high just before it asserts the stop P condition This sequence terminates a read cyc...

Страница 21: ...D package is a 14 mm 14 mm 1 mm TQFP outline with 0 5 mm lead pitch The PowerPAD package has a specially designed die mount pad that offers improved thermal capability over typical TQFP packages of the same outline The TI 100 terminal TQFP PowerPAD package offers a backside solder plane that connects directly to the die mount pad for enhanced thermal conduction If traces or vias are located under ...

Страница 22: ...al TQFP PowerPAD package Table 1 TI 100 Terminal TQFP 14 14 1 mm 0 5 mm Lead Pitch PARAMETER PowerPAD NOT CONNECTED TO PCB THERMAL PLANE PowerPAD CONNECTED TO PCB THERMAL PLANE see Note 15 RθJA Junction to ambient thermal resistance see Notes 15 16 17 and 18 73 7 C W 22 5 C W PD Package power dissipation see Notes 15 16 17 and 18 1 08 W 3 55 W NOTES 15 Specified with the PowerPAD bond pad on the b...

Страница 23: ...or use in specified lead free processes Pb Free RoHS Exempt This component has a RoHS exemption for either 1 lead based flip chip solder bumps used between the die and package or 2 lead based die adhesive used between the die and leadframe The component is otherwise considered Pb Free RoHS compatible as defined above Green RoHS no Sb Br TI defines Green to mean Pb Free RoHS compatible and free of ...

Страница 24: ......

Страница 25: ......

Страница 26: ......

Страница 27: ...ice TI is not responsible or liable for any such statements TI products are not authorized for use in safety critical applications such as life support where a failure of the TI product would reasonably be expected to cause severe personal injury or death unless officers of the parties have executed an agreement specifically governing such use Buyers represent that they have all necessary expertis...

Результаты поиска

Содержание PanelBus TFP503

Отзывы:

Бренды по названию

Популярные бренды

Texas Instruments PanelBus TFP503, Руководство пользователя

Результаты поиска

Содержание PanelBus TFP503

Отзывы:

Бренды по названию

Популярные бренды