PanelBus
SLDS149 − AUGUST 2004
11
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
timing diagrams (continued)
Figure 9. Delay From PD Low to High Before
Inputs Are Active
Figure 10. Minimum Time PD Low
PD
DFO, ST, PIXS, STAG,
Rx[2:0]+, Rx[2:0]−,
OCK_INV
VIH
td(PDLA)
td(PDLM)
PD
VIL
tsk(CC)
50%
50%
TX2
TX1
TX0
Figure 11. Analog Input Channel-to-Channel Skew
t(HSC)
t(FSC)
DE
SCDT
Figure 12. Time Between DE Transitions to SCDT Low and SCDT High
