Texas Instruments OMAP36 Series, Техническое справочное руководство

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SDRAM Controller (SDRC) Subsystem
Table 10-101. Mobile DDR SDRAM AC Timing Parameters (continued)
AC Timing Parameter Description Duration (ns)
tRC Row cycle time 67.5 (or 9 tCK)
tRAS Row active time 45 (or 6 tCK)
tRCD nRAS to nCAS delay time 22.5 (or 3 tCK)
tRRD Row active to row active delay time 15 (or 2 tCK)
The latency to access another row in the same bank depends on tRP and tRAS timings because a
precharge command followed by an active command must be issued. Therefore, 6 tCK are needed to
close the current row and open another one.
When accessing another bank, the latency to access another row depends on tRAS timing only because
the closing of the current row is not mandatory. In other words only an active command must be issued.
Therefore, 3 tCK are needed to open another row in a different bank.
Single initiator use case:
When the initiator wants to access a page in a bank for the first time, it opens only this page. It takes 3
tCK. When the initiator is done with this page, it closes this page and opens another one. It takes 6
tCK.
Two initiators use case:
When one initiator wants to access a page in the same bank, it must necessarily close the current
page and open the page it wants to access. It takes 6 tCK.
When one initiator wants to access a page this time in another bank, there can be less page opening
and closing. For instance, if the initiator wants to open a page in another bank where no page is open,
it takes only 3 tCK, rather than 6 tCK if it was another page in the same bank.
10.2.4.4.5 Data Multiplexing During Write Operations
10.2.4.4.5.1 External Bus Combinations
The SDRC pin allocation scenarios are provided in Table 10-102 . These scenarios are defined on a
per-CS basis for maximum flexibility. The pin allocation configurations allow implementation of
combinations of the 16-/32-bit external interfaces listed in this table. The data multiplexer receives a 64-bit
word from the SDRAM command queue and partitions the data into a series of 16-bit or 32-bit accesses.
The data multiplexer also steers the data to the appropriate data lane. The data partitioning and data
steering are determined by the SDRC.
SDRC_SHARING [11:9] CS0MUXCFG and
SDRC. SDRC_SHARING [14:12] CS1MUXCFG fields.
Table 10-102. SDRC Data Lane Configurations
Device sdrc_d[31:24] sdrc_d[23:16] sdrc_d[15:8] sdrc_d[7:0]
pins
DataLane[31:16] DataLane[15:0]
DQS3 DQS2 DQS1 DQS0
DQM3 DQM2 DQM1 DQM0 SDRC. SDRC_SHARING [14:9]
CSnMUXCFG field
D[31:0] 0x0, 0x1
D[15:0] 0x2, 0x7
D[15:0] 0x3
0x4, 0x5, 0x6: Reserved
2253 SWPU177N – December 2009 – Revised November 2010 Memory Subsystem
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