Texas Instruments OMAP36 Series, Техническое справочное руководство

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L3 Interconnect
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9.2.3.4.2 Time-Out
A time-out mechanism can be enabled in the target agent and initiator agent register. When the
mechanism is enabled for a target agent or initiator agent and commands are not accepted or responses
are not returned within the expected delay, the L3 interconnect generates an error event.
The error is logged in the target agent REQ_TIMEOUT bit L3_TA_AGENT_STATUS [8] for a target agent
time-out, the BURST_TIMEOUT bit L3_IA_AGENT_STATUS [16] bit for an initiator burst time-out, and the
RESP_TIMEOUT bit L3_IA_AGENT_STATUS [8] for an initiator response time-out. The affected agent
enters an error state that causes it to send error responses to any new request. To recover from this state,
the target agent must be reset by system software.
The time-out is counted starting from the moment a command is presented to the target, whatever the
target response to this command is. The L3 interconnect implements a centralized time-base circuit that
broadcasts a set of four periodic pulse signals to all connected target agents. These four signals are
referred to as 1x time-base, 4x time-base, 16x time-base, and 64x time-base.
The time-base circuit offers four possible sets of four time-base signals selected by programming the
TIMEOUT_BASE field
L3_RT_NETWORK_CONTROL [10:8]. Table 9-27 lists all of the values in the
number of L3 clock cycles.
Each target agent can be programmed to refer to one of the four time-base signals. A time-out condition is
detected when either the command acceptance or the response is not received after a delay of between
one and three time-base periods. After the time-out is detected and logged, the behavior of the attached
module is ignored. A new request to the module arriving at the timed-out target agent receives an error
response. If the request is addressed to the agent internal registers, it is processed normally.
To recover from a time-out error, the software is assumed to reset first the faulty module using its internal
soft-reset bit, and then the agent using software reset.
Table 9-27. L3 Timeout Register Target and Agent Programming
REQ_TIMEOUT[2:0], BURST_TIMEOUT[2:0], and RESP_TIMEOUT[2:0]
TIMEOUT_BASE[2:0] 0 1 2 3 4
0 All L3 time-out features are disabled.
1 Locally disabled 64 256 1024 4096
2 256 1024 4096 16384
3 1024 4096 16384 65536
4 4096 16384 65536 262144
9.2.3.4.3 Error Steering
The error reporting structure consist of errors logged individually in the initiator or TAs. Some errors can
be enabled and reported out-of-band by setting the following bits to 1:
•
L3_IA_AGENT_CONTROL .BURST_TIMEOUT_REP bit for burst time-out
• L3_IA_AGENT_CONTROL .RESP_TIMEOUT_REP bit for response time-out
• L3_TA_AGENT_CONTROL .REQ_TIMEOUT_REP bit for request time-out
• L3_TA_AGENT_CONTROL .SERROR_REP bit for request time-out
Setting the L3_IA_AGENT_CONTROL .ALL_INBAND_ERROR_REP bit causes all in-band errors
returned to the IA to be reported out-of-band.
IAs connected to processors capable of generating the debug-flagged requests (the MPU and IVA2.2
subsystems) use error steering. Any error linked to an application (nondebug) request is qualified as
primary; any error linked to a debug request is qualified as secondary. Setting the
IA.INBAND_ERROR_PRIMARY_REP or INBAND_ERROR_SECONDARY_REP bit to 1 allows the
reporting of in-band to out-of-band primary and secondary errors.
The level of the current error is indicated in SECONDARY bit
L3_IA_ERROR_LOG [30]. If an error
occurs while another error is pending, the following occurs:
• If the pending error is primary, the new error is discarded at the IA level. MULTI bit
L3_IA_ERROR_LOG [31] is set in the initiator error log register to indicate that another error has
been detected; no further information can be stored.
2016 Interconnect SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated