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Display Subsystem Functional Description
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7.4.7.2
Luma Stage
The luma stage includes a luma pipeline delay, luma shaping, 2x interpolation filter, and luma variable
delay. The luma pipeline delay block is used to match luma path length to chroma path length. In the luma
gain shaper, a programmable gain is first applied to the luminance data output. The luminance gain is
defined by the DSS.
register. Horizontal sync, vertical sync, and setup insertion are then
performed.
Black level and blank level are programmable through the DSS.
and
registers. All the transition edges of the luminance signal, such as sync
edges and active video edges, are properly shaped and filtered to keep the bandwidth within the
standards.
After all required components of the luminance signal are added, the resulting signal is low-passed and
interpolated to 2x-pixel rate. This 2x interpolation simplifies the external analog reconstruction filter design
and improves the signal-to-noise ratio.
7.4.7.3
Chroma Stage
The chroma stage includes a low-pass filter, first-stage 2x interpolation, chroma gain shaper, and
second-stage 2x interpolation. A pair of programmable gains adjusts the time-multiplexed U/V signal. The
gains for U and V are independently controlled by the DSS.
and DSS.
register bits.
7.4.7.4
Subcarrier and Burst Generation
The encoder uses a 32-bit subcarrier increment to synthesize the subcarrier. The value of the subcarrier
increments required to generate the desired subcarrier frequency for NTSC and PAL format is found by:
S_CARR = ROUND ([F
sc
/F
clkenc
] x 2
32
)
where:
F
sc
= Frequency of the subcarrier
F
clkenc
= Frequency of the internal video encoder
The DSS.
register controls the subcarrier frequency. The DSS.
register
controls the phase of the subcarrier. The phase of the color subcarrier is reset to DSS.
presents the
register values depending the standard and pixel type used.
Table 7-40. VENC_S_CARR Register Recommended Values
Subcarrier
register
Standard
Pixel Type
Frequency (Fsc)
Fclkenc (MHz)
value (hexa)
(MHz)
NTSC-M, J
ITU-R601
3.579545
27
0x21F07C1F
PAL-M
ITU-R601
3.5756083125
27
0x21E6EFE3
PAL-B, D, G, H, I
ITU-R601
4.43361875
27
0x2A098ACB
NTSC-M, J
Square pixel
3.579545
24.5454
0x25555555
PAL-M
Square pixel
3.579561149
24.5454
0x1F15C01E
PAL-B, D, G, H, I
Square pixel
4.43361875
29.50
0x26798C0C
CAUTION
In square pixel mode, an external clock generator is needed to provide
sampling frequencies (49.09 MHz for NTSC square pixel or 59 MHz for PAL
square pixel).
The color subcarrier reset has four modes:
•
No reset
1692
Display Subsystem
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated
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