Texas Instruments OMAP36 Series, Техническое справочное руководство

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cam_hs
cam_vs
cam_fld
cam_d
cam_pclk
0 1 2 3 4 5 6 0 1 2 3 4 5 0 1 2 3 4 5 6
8 pulses after
end of frame
required
4 pulses
before start
of frame
required
6
Extra pulses
allowed but not
required during
blanking
cam_hs must be
inactive for at
least one clock
pulse between
2 lines
cam_hs must be
active for at
least one clock
pulse to qualify
start of line
cam_vs must be
active for at
least one clock
pulse to qualify
start of frame
Extra pulses
between frames
allowed but not
required
Data sampled on rising
edge in this diagram.
Programmable see
register manual section.
camisp-132
camisp-100
Timing of JPEG compressed data in free running clock mode
cam_vs
cam_hs
cam_pclk
cam_d
VS
WEN
HS
PCLK
A
t
th
e
in
p
u
t
o
f
C
C
D
C
Public Version
www.ti.com
Camera ISP Environment
Figure 6-4. Camera ISP SYNC Mode Clock Gating
6.2.4.2 Camera ISP Parallel Generic Configuration: JPEG Sensor Connection on the Parallel Interface
Some camera modules integrate an image-signal processor (ISP) and a JPEG encoder. The CCDC can
interface with these camera modules and transfer the received JPEG stream to memory.
To use this mode, set the ISP_CTRL [30] JPEG_FLUSH bit.
Figure 6-5 shows timing diagrams for an JPEG stream.
Figure 6-5. Camera ISP JPEG Stream Timing Diagrams
CAUTION
The bridge cannot be used for JPEG sensor connections.
6.2.4.3 Camera ISP ITU-R BT.656 Protocol and Data Formats (8, 10 Bits)
CAUTION
The ITU-R BT.656 mode cannot be used when the bridge is enabled.
The camera ISP interface supports data in ITU-R BT.656 format.
1097 SWPU177N – December 2009 – Revised November 2010 Camera Image Signal Processor
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