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IVA2.2 Subsystem Register Manual
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Bits Field Name Description Type Reset
5:4 MPGMOD Additional MPEG mode RW 0x0
0: MPEG4 normal
1: MPEG4 data partitioning
2: MPEG4 RVLC
3: WMV9 (decode only)
Field active when
VLCD_MODE (5:4) = MPEG4
3 SCANTYPE SCAN mode RW 0x0
0: SCAN type is selected by VLCD_MODE (9:8)
1: SCAN type is selected by Q/IQ_CONFIG1 to Q/IQ_CONFIG5
2 MP2ENCDEC MPEG2 encode/decode RW 0x0
0: MPEG1 VLCD_MODE (5:4) = MPEG1
1: MPEG2 VLCD_MODE (5:4) = MPEG1
1 MP4ESC MPEG4 escape encoding RW 0x0
0: Escape3 only(DSC25)
1: Escape1,2 and 3
0 CLKON Dynamic clock on/off control RW 0x0
0: On
1: Off
Table 5-625. Register Call Summary for Register VLCD_CTRL
IVA2.2 Subsystem Register Manual
• iVLCD Register Mapping Summary : [0]
• iVLCD Register Descriptions : [1] [2]
Table 5-626. VLCD_VLD_PREFIX_DC
Address Offset 0x0000 1100
Physical Address 0x0008 1100 Instance iVLCD
Description This register sets the ring buffer end address.
Type RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED NBITS_DC_Y NBITS_DC_UV
RESERVED
Bits Field Name Description Type Reset
31:13 RESERVED Write 0s for future compatibility RW 0x0
Read returns 0
12:8 NBITS_DC_Y Sets the number of prefix bits of control table for the RW 0x00
DCY term as input to the UVLD.
7:5 RESERVED Write 0s for future compatibility RW 0x0
Read returns 0
4:0 NBITS_DC_UV Sets the number of prefix bits of control table for the RW 0x00
DCUV term as input to the UVLD.
Table 5-627. Register Call Summary for Register VLCD_VLD_PREFIX_DC
IVA2.2 Subsystem Register Manual
• iVLCD Register Mapping Summary : [0]
1032 IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010
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