Signal Description
2-3
MSP53C391 Hardware Description
2.2
Signal Description
Table 2–1. MSP53C391 Signal Description
Pin
Description
Name
No.
DAC+
DAC–
12
13
PDM-style DAC used for speech output.
DATA3/BUSY
16
BUSY signal can be obtained on DATA 3 during read operation. A high signal
indicates that the MSP53C391 is
not busy and ready to accept data. A low signal
indicates that the MSP53C391 is busy and the master should not write any
command or data to MSP53C391.
DATA2/EOS
1
The EOS signal can be obtained on the DATA2 pin during a read operation. This
signal is normally low, but goes high when the end-of-speech code is reached in
the data stream.
STROB
15
This is an active low strobe signal for the reading and writing operation from the
master microprocessor. The data to be read is available when the strobe is active
(low) for the read operation. The data on the data line is latched into the
MSP53C391 on the raising edge of the strobe signal for the write operation.
R/W
7
Read/write signal from master microprocessor. A high signal for a read operation
and a low signal for a write operation.
IRQ
14
When the data latched into the MSP53C391 is read and the MSP53C391 device is
ready to accept more data, a negative edge interrupt signal is generated to
interrupt the master. For proper operation of the interrupt function, a negative edge
triggered external interrupt input pin is required on the master microprocessor.
EOS
6
This is an active high output signal that is asserted when end-of-speech is
reached. It indicates that the speech synthesis process is finished. When a high is
detected on the EOS line by the master microprocessor, dummy bytes are written
to the MSP53C391 to reset the EOS. The next transfer can then be initiated after
the EOS was de-asserted. EOS also appears on the DATA2 pin during a read
operation for adopting different interfacing methods.
OUT1–2
5,4
General-purpose output port that can be controlled by the master microprocessor.
DATA 0–3
3,2,1,16 4-bit bidirectional data line
INIT
9
Reset signal. A low pulse to reset the chip. It can also be used to stop the
MSP53C391 operation during speech synthesis. Following the rising edge of the
INIT pulse, a delay of up to 5 ms will be required to permit the MSP53C391 to com-
pletely initialize its internal condition.
Содержание MSP53C391
Страница 1: ...MSP53C391 and MSP53C392 Speech Synthesizers User s Guide May 2000 SPSU016A Printed on Recycled Paper ...
Страница 4: ...iv ...
Страница 62: ...C 1 Appendix A Listing of FMequM2 inc Topic Page C 1 Listing of FMequM2 inc C 2 Appendix C ...
Страница 78: ...E 1 Appendix A Listing of FM2INTR1 inc Topic Page E 1 Listing of FM2INTR1 inc E 2 Appendix E ...
Страница 98: ...F 1 Appendix A MSP53C391 and MSP53C392 Data Sheet Topic Page F 1 MSP53C391 MSP53C392 F 2 Appendix F ...
Страница 99: ...MSP53C31 and MSP53C32 Data Sheet F 2 F 1 MSP53C31 and MSP53C32 Data Sheet ...