Texas Instruments MSP430F42 series Скачать руководство пользователя страница 39 | Manualshive

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MSP430F42x

MIXED SIGNAL MICROCONTROLLER

SLAS421A − APRIL 2004 − REVISED JUNE 2007

39

POST OFFICE BOX 655303

•

DALLAS, TEXAS 75265

Data Sheet Revision History

Literature

Number

Summary

SLAS421

Production datasheet release

SLAS421A

Updated functional block diagram (page 3)
Clarified test conditions in recommended operating conditions table (page 17)
Changed “Supply voltage during program execution; SD16 disabled, SVS enabled, and PORON = 1” MIN value from 2.2 V
to 2.0 V (page 17)
Clarified test conditions for I

(LPM0)

in supply current into AV

CC

+ DV

CC

table (page 18)

Clarified test conditions in USART0 table (page 21)
Changed PSRR to AC PSRR in SD16 analog performance table (page 29)
Added DC PSR in SD16, built-in voltage reference table (page 30)
Added t

ON

parameter to SD16, built-in voltage reference and SD16, built-in reference output buffer tables (page 30)

Changed t

CPT

maximum value from 4 ms to 10 ms in Flash memory table (page 31)

NOTE: Page and figure numbers refer to the respective document revision.

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Содержание MSP430F42 series

Страница 1: ...in portable measurement applications The device features a powerful 16 bit RISC CPU 16 bit registers and constant generators that contribute to maximum code efficiency The digitally controlled oscilla...

Страница 2: ...TACLK ACLK S28 P2 3 SVSIN P2 4 UTXD0 P2 5 URXD0 RST NMI TCK TMS TDI TCLK TDO TDI P1 0 TA0 P1 1 TA0 MCLK P1 2 TA1 S31 P1 3 SVSOUT S30 P1 4 S29 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 S20...

Страница 3: ...I P1 Flash 32KB 16KB 8KB RAM 1KB 512B 256B Watchdog WDT 15 16 Bit Timer_A3 3 CC Reg Port 1 8 I O Interrupt Capability POR SVS Brownout Basic Timer 1 1 Interrupt Vector LCD 128 Segments 1 2 3 4 MUX fLC...

Страница 4: ...gital I O slave transmit enable USART0 SPI mode S0 12 O LCD segment output 0 S1 13 O LCD segment output 1 S2 14 O LCD segment output 2 S3 15 O LCD segment output 3 S4 16 O LCD segment output 4 S5 17 O...

Страница 5: ...S31 51 I O General purpose digital I O Timer_A Capture CCI1A CCI1B input Compare Out1 output LCD segment output 31 See Note 1 P1 1 TA0 MCLK 52 I O General purpose digital I O Timer_A Capture CCI0B in...

Страница 6: ...CPU clock Four of the registers R0 to R3 are dedicated as program counter stack pointer status register and constant generator respectively The remaining registers are general purpose registers Perip...

Страница 7: ...ve D Low power mode 0 LPM0 CPU is disabled ACLK and SMCLK remain active MCLK is available to modules FLL loop control remains active D Low power mode 1 LPM1 CPU is disabled ACLK and SMCLK remain activ...

Страница 8: ...SD16OVIFG SD16CCTLx SD16IFG see Notes 1 and 2 Maskable 0FFF8h 12 0FFF6h 11 Watchdog Timer WDTIFG Maskable 0FFF4h 10 USART0 Receive URXIFG0 Maskable 0FFF2h 9 USART0 Transmit UTXIFG0 Maskable 0FFF0h 8...

Страница 9: ...s configured in interval timer mode OFIE Oscillator fault interrupt enable NMIIE Nonmaskable interrupt enable ACCVIE Flash access violation interrupt enable URXIE0 USART0 UART and SPI receive interrup...

Страница 10: ...16KB 0FFFFh 0FFE0h 0FFFFh 0C000h 32KB 0FFFFh 0FFE0h 0FFFFh 08000h Information memory Size 256 Byte 010FFh 01000h 256 Byte 010FFh 01000h 256 Byte 010FFh 01000h Boot memory Size 1kB 0FFFh 0C00h 1kB 0FFF...

Страница 11: ...Segments A and B can be erased individually or as a group with segments 0 n Segments A and B are also called information memory D New devices may have some bytes programmed in the information memory n...

Страница 12: ...ff The supply voltage supervisor SVS circuitry detects if the supply voltage drops below a user selectable level and supports both supply voltage supervision the device is automatically reset and supp...

Страница 13: ...CCI0A 53 P1 0 52 P1 1 TA0 CCI0B CCR0 TA0 DVSS GND CCR0 TA0 DVCC VCC 51 P1 2 TA1 CCI1A 51 P1 2 51 P1 2 TA1 CCI1B CCR1 TA1 DVSS GND CCR1 TA1 DVCC VCC 45 P2 0 TA2 CCI2A 45 P2 0 ACLK internal CCI2B CCR2...

Страница 14: ...t high word RESHI 013Ch Result low word RESLO 013Ah Second operand OP2 0138h Multiply signed accumulate operand1 MACS 0136h Multiply accumulate operand1 MAC 0134h Multiply signed operand1 MPYS 0132h M...

Страница 15: ...Reserved 0BCh Reserved 0BDh Reserved 0BEh Reserved 0BFh LCD LCD memory 20 LCDM20 0A4h LCD memory 16 LCDM16 0A0h LCD memory 15 LCDM15 09Fh LCD memory 1 LCDM1 091h LCD control and mode LCDCTL 090h USAR...

Страница 16: ...flag P2IFG 02Bh Port P2 direction P2DIR 02Ah Port P2 output P2OUT 029h Port P2 input P2IN 028h Port P1 Port P1 selection P1SEL 026h Port P1 interrupt enable P1IE 025h Port P1 interrupt edge select P1I...

Страница 17: ...N 1 VCC AVCC DVCC VCC see Note 1 and Note 2 MSP430F42x 2 0 3 6 V Supply voltage during program execution SD16 enabled or during programming of flash memory VCC AVCC DVCC VCC MSP430F42x 2 7 3 6 V Suppl...

Страница 18: ...5 2 0 I Low power mode LPM3 see Note 2 TA 25 C V 3 V 1 6 2 1 A I LPM3 Low power mode LPM3 see Note 2 TA 60 C VCC 3 V 1 7 2 2 A TA 85 C 2 0 2 6 TA 40 C 0 1 0 5 I LPM4 Low power mode LPM4 see Note 2 TA...

Страница 19: ...ycles leakage current see Note 1 PARAMETER TEST CONDITIONS MIN NOM MAX UNIT Ilkg P1 x Leakage Port P1 Port 1 V P1 x see Note 2 V 3 V 50 nA Ilkg P2 x Leakage current Port P2 Port 2 V P2 x see Note 2 VC...

Страница 20: ...VOL Low Level Output Voltage V 0 10 20 30 40 50 0 0 0 5 1 0 1 5 2 0 2 5 3 0 3 5 VCC 3 V P2 1 TYPICAL LOW LEVEL OUTPUT CURRENT vs LOW LEVEL OUTPUT VOLTAGE TA 25 C TA 85 C OL I Typical Low level Output...

Страница 21: ...RT0 see Note 1 PARAMETER TEST CONDITIONS MIN NOM MAX UNIT t USART0 deglitch time VCC 3 V SYNC 0 UART mode 150 280 500 ns NOTE 1 The signal applied to the USART0 receive signal terminal URXD0 should me...

Страница 22: ...POR Brownout Reset BOR vs Supply Voltage V CC drop V 0 0 5 1 1 5 2 0 001 1 1000 V 3 V Typical Conditions 1 ns 1 ns tpw Pulse Width s tpw Pulse Width s cc VCC 3 V VCC drop tpw Figure 7 VCC drop Level W...

Страница 23: ...ge applied on P2 3 VLD 15 4 4 10 4 mV VLD 1 1 8 1 9 2 05 VLD 2 1 94 2 1 2 25 VLD 3 2 05 2 2 2 37 VLD 4 2 14 2 3 2 48 VLD 5 2 24 2 4 2 6 VLD 6 2 33 2 5 2 71 VCC dt 3 V s see Figure 9 VLD 7 2 46 2 65 2...

Страница 24: ...0 SVS is Active Undefined 0 1 Brownout 0 1 0 1 Set POR Brownout Region SVS Circuit is Active From VLD to VCC V B_IT SVS out Vhys SVS_IT Vhys B_IT td BOR td SVSon td SVSR td BOR SVS_IT Figure 9 SVS Re...

Страница 25: ...COPLUS 1 3 V 1 3 2 2 3 5 MHz f DCO 27 FN_8 FN_4 0 FN_3 1 FN_2 x DCOPLUS 1 3 V 10 3 17 9 28 5 MHz f DCO 2 FN_8 0 FN_4 1 FN_3 FN_2 x DCOPLUS 1 3 V 2 1 3 4 5 2 MHz f DCO 27 FN_8 0 FN_4 1 FN_3 FN_2 x DCOP...

Страница 26: ...CO Tap S n Stepsize Ratio between DCO Taps Min Max 1 07 1 06 Figure 12 DCO Tap Step Size DCO Frequency Adjusted by Bits 29 to 25 in SCFI1 N DCO FN_2 0 FN_3 0 FN_4 0 FN_8 0 FN_2 1 FN_3 0 FN_4 0 FN_8 0...

Страница 27: ...is CXIN x CXOUT CXIN CXOUT It is independent of XTS_FLL 2 To improve EMI on the low power LFXT1 oscillator particularly in the LF mode 32 kHz the following guidelines must be observed Keep as short a...

Страница 28: ...bled 3 V 0 5 MHz SD16 analog input range see Note 1 PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT SD16GAINx 1 SD16REFON 1 500 Differential input SD16GAINx 2 SD16REFON 1 250 V Differential input volta...

Страница 29: ...V 0 2 FSR EOS Offset error SD16GAINx 32 3 V 1 5 FSR dE dT Offset error temperature SD16GAINx 1 3 V 4 20 ppm dEOS dT temperature coefficient SD16GAINx 32 3 V 20 100 ppm FSR _C CMRR Common mode SD16GAIN...

Страница 30: ...ejection VREF VCC SD16REFON 1 SD16VMIDON 0 VCC 2 5 V to 3 6 V 200 V V NOTES 1 There is no capacitance required on VREF However a capacitance of at least 100nF is recommended to reduce any reference vo...

Страница 31: ...64 byte flash block This parameter applies to all programming methods individual word byte write and block write modes 2 The mass erase duration generated by the flash timing generator is at least 11...

Страница 32: ...Interrupt Edge Select P1IES x P1SEL x P1IE x P1IFG x P1IRQ x EN Set Q 0 1 1 0 Pad Logic 0 Input 1 Output Bus keeper CAPD x PnSEL x PnDIR x Direction From Module PnOUT x Module X OUT PnIN x PnIE x PnIF...

Страница 33: ...EL 2 P1DIR 2 P1OUT 2 P1IN 2 P1IE 2 P1IFG 2 P1IES 2 P1SEL 3 P1DIR 3 P1OUT 3 P1IN 3 P1IE 3 P1IFG 3 P1IES 3 P1SEL 4 P1DIR 4 P1OUT 4 P1IN 4 P1IE 4 P1IFG 4 P1IES 4 P1SEL 5 P1DIR 5 P1OUT 5 P1IN 5 P1IE 5 P1I...

Страница 34: ...1 1 0 PnSel x PnDIR x Dir Control from module PnOUT x Module X OUT PnIN x PnIE x PnIFG x PnIES x Module X IN 0 Port active 1 Segment xx function active P2Sel 0 P2DIR 0 P2Sel 1 P2DIR 1 P2DIR 0 DCM_UCLK...

Страница 35: ...Output Bus keeper CAPD x PnSEL x PnDIR x Direction From Module PnOUT x Module X OUT PnIN x PnIE x PnIFG x PnIES x Module X IN P2SEL 2 P2DIR 2 P2OUT 2 P2IN 2 P2IE 2 P2IFG 2 P2IES 2 P2SEL 3 P2DIR 3 P2OU...

Страница 36: ...Control From Module P2DIR x P2SEL x Bus Keeper 0 1 0 Input 1 Output Node Is Reset With PUC PUC NOTE x Bit identifier 6 to 7 for port P2 without external pins P2Sel x P2DIR x DIRECTION CONTROL FROM MO...

Страница 37: ...5265 APPLICATION INFORMATION JTAG pins TMS TCK TDI TCLK TDO TDI input output with Schmitt trigger or output TDI TDO TMS TDI TCLK TDO TDI Controlled by JTAG TCK TMS TCK DVCC Controlled by JTAG Test JTA...

Страница 38: ...wer consumption Activation of the fuse check mode occurs with the first negative edge on the TMS pin after power up or if the TMS is being held low during power up The second positive edge on the TMS...

Страница 39: ...disabled SVS enabled and PORON 1 MIN value from 2 2 V to 2 0 V page 17 Clarified test conditions for I LPM0 in supply current into AVCC DVCC table page 18 Clarified test conditions in USART0 table pa...

Страница 40: ...ces including the requirement that lead not exceed 0 1 by weight in homogeneous materials Where designed to be soldered at high temperatures TI Pb Free products are suitable for use in specified lead...

Страница 41: ...3 NOM 0 25 0 45 0 75 Seating Plane 0 05 MIN Gage Plane 0 27 33 16 48 1 0 17 49 64 SQ SQ 10 20 11 80 12 20 9 80 7 50 TYP 1 60 MAX 1 45 1 35 0 08 0 50 M 0 08 0 7 NOTES A All linear dimensions are in mil...

Страница 42: ...iness practice TI is not responsible or liable for any such statements TI products are not authorized for use in safety critical applications such as life support where a failure of the TI product wou...

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