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Debugging (C-SPY)
19. C-SPY utilizes the system clock to control the device during debugging. Therefore, device counters,
etc., that are clocked by the Main System Clock (MCLK) will be affected when C-SPY has
control of the device. Special precautions are taken to minimize the effect upon the Watchdog Timer.
The CPU core registers are preserved. All other clock sources (SMCLK, ACLK) and peripherals
continue to operate normally during emulation. In other words, the Flash Emulation Tool is a
partially intrusive tool.
Devices that support clock control (Emulator
→
Advanced
→
Clock Control) can further minimize these
effects by selecting to stop the clock(s) during debugging (see FAQ Debugging #24 ).
20. There is a time after C-SPY performs a reset of the device (when the C-SPY session is first
started, when the Flash is reprogrammed (via Init New Device), and when JTAG is resynchronized
(Resynchronize JTAG)) and before C-SPY has regained control of the device that the device will
execute code normally. This behavior may have side effects. Once C-SPY has regained control of
the device, it will perform a reset of the device and retain control.
21. When programming the Flash, do not set a breakpoint on the instruction immediately following
the write to Flash operation. A simple workaround to this limitation is to follow the write to Flash
operation with a NOP, and set a breakpoint on the instruction following the NOP (see FAQ
Debugging
#23 ).
22. The Dump Memory length specifier is restricted to four hexadecimal digits (0 to FFFF). This
limits the number of bytes that can be written from 0 to 65535. Consequently, it is not possible to write
memory from 0 to 0xFFFF inclusive, as this would require a length specifier of 65536 (or 10000h).
23. Multiple internal machine cycles are required to clear and program the Flash memory. When single
stepping over instructions that manipulate the Flash, control is given back to C-SPY before these
operations are complete. Consequently, C-SPY updates its memory window with erroneous
information. A workaround to this behavior is to follow the Flash access instruction with a NOP, and
then step past the NOP before reviewing the effects of the Flash access instruction (see FAQ
Debugging #21 ).
24. Peripheral bits that are cleared when read during normal program execution (i.e., interrupt flags)
are cleared when read while being debugged (i.e., memory dump, peripheral registers).
When using certain MSP430 devices (such as MSP430F15x/16x and MSP430F43x/44x devices), bits
do not behave this way (i.e., the bits are not cleared by C-SPY read operations).
25. C-SPY cannot be used to debug programs that execute in the RAM of 'F12x and 'F41x devices.
A work around to this limitation is to debug programs in Flash.
26. While single stepping with active and enabled interrupts, it can appear that only the interrupt
service routine (ISR) is active (i.e., the non-ISR code never appears to execute, and the single step
operation always stops on the first line of the ISR). However, this behavior is correct because the
device alwayses process an active and enabled interrupt before processing non-ISR (i.e., mainline)
code. A workaround for this behavior is, while within the ISR, to disable the GIE bit on the stack so that
interrupts are disabled after exiting the ISR. This permits the non-ISR code to be debugged (but
without interrupts). Interrupts can later be reenabled by setting GIE in the status register in the Register
window.
On devices with the clock control emulation feature, it may be possible to suspend a clock between
single steps and delay an interrupt request (Emulator
→
Advanced
→
Clock Control).
27. The base (decimal, hexadecimal, etc.) property of Watch Window variables is not preserved
between C-SPY sessions; the base reverts to Default Format.
28. On devices equipped with a Data Transfer Controller (DTC), the completion of a data transfer cycle
preempts a single step of a low-power mode instruction. The device advances beyond the
low-power mode instruction only after an interrupt is processed. Until an interrupt is processed, it
appear that the single step has no effect. A workaround to this situation is to set a breakpoint on the
instruction following the low-power mode instruction, and then execute (Go) to this breakpoint.
29. The transfer of data by the Data Transfer Controller (DTC) may not stop precisely when the
DTC is stopped in response to a single step or a breakpoint. When the DTC is enabled and a
single step is performed, one or more bytes of data can be transferred. When the DTC is enabled and
configured for two-block transfer mode, the DTC may not stop precisely on a block boundary when
stopped in response to a single step or a breakpoint.
30. The C-SPY Register window supports instruction cycle length counters. The cycle counter is only
active while single stepping. The count is reset when the device is reset, or the device is run (Go). The
count can be edited (normally set to zero) at any time.
SLAU138F – June 2004 – Revised March 2007 Frequently Asked Questions 35
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