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EVM Setup and Operation
10
SGLU009 – November 2016
Copyright © 2016, Texas Instruments Incorporated
Revision History
Figure 17. TPS3820-33-Q1 Watchdog Timeout t
tout
, From
WDI Falling to RESET Falling
Figure 18. TPS3824-30-Q1 Watchdog Timeout t
tout
, From
WDI Falling to RESET Falling
4.4
Reset Outputs (RESET and RESET)
All TPS382x-Q1 devices offer an active-low RESET signal, while TPS3824-Q1 and TPS3825-Q1 offer an
additional active-high RESET signal. The EVM has a 2-pin header for each RESET and RESET pin, with
both header pins shorted together. The reset signal will be asserted (low for RESET pins and high for
RESET pins) when the supply voltage drops below the threshold voltage, when MR is pulled low, or when
a trigger is not detected on the WDI pin for time t
tout
. When VDD is higher than the threshold voltage, the
MR pin is pulled high or floating, and WDI is triggered or left floating, then the reset pins will remain
de-asserted
Revision History
DATE
REVISION
NOTES
November 2016
*
Initial Release