Board Layout
5
Board Layout
This section describes the board layout of the LP8754EVM. See LP8754 data sheet for specific PCB
layout recommendations.
The board is constructed on a 4-layer PCB.
shows the top view of the entire board and
through
show the component placement, layout and 3D view close to the LP8754 device. Vias
under the LP8754 are filled microvias from top layer to the GND plane (layer 2), buried vias between 2nd-
layer and 3rd-layer and microvias from 3rd-layer to bottom layer.
Routing is mostly done on top and bottom layers. Top layer contains the large copper area connecting the
VOUT pads of the inductors and output capacitors together and to the load terminals. 2nd layer is the
ground plane and 3rd layer is the VIN plane. Also the bottom layer contains large copper area filled with
ground. Input capacitors are placed as close to the LP8754 as possible for keeping the critical VIN and
GND traces short. Output capacitors and inductors are placed around the input capacitors. Using the 0603
size input and output capacitors and 2.0 mm x 1.2 mm size inductors the total solution size is about 82.5
mm
2
.
Figure 4. Top view of the LP8754EVM
11
SNVU369 – August 2014
The LP8754 Evaluation Module
Copyright © 2014, Texas Instruments Incorporated
