Setup
5
SNAU114D – March 2006 – Revised June 2016
Copyright © 2006–2016, Texas Instruments Incorporated
Using the LMX2485E & LMX2487E Evaluation Board
1.2
Loop Filter Values
TI’s Clock Design Tool can be used to optimize PLL phase noise/jitter for given specifications. See
http://www.ti.com/tool/codeloader
1.3
RF PLL Loop Filter
Table 4. RF PLL Loop Filter Parameters
LMX2485E
LMX2487E
VCO Used
Crystek CVCO55CL
Crystek CVCO55BH
VCO Gain
8 MHz/V
100 MHz/V
VCO Input Capacitance
330 pF
10 pF
Nominal Output Frequency
60 to 80 MHz
4100 to 4300 MHz
Phase Margin
44º
50º
Loop Bandwidth
8.7 kHz
15 kHz
Reference Clock Frequency
50 MHz
100 MHz
K
φ
(Charge Pump)
16X (1520
μ
A)
8X (760
μ
A)
Phase Detector Freq
2000 kHz
20000 kHz
PLL Supply
3.3 V from LDO
3.3 V from LDO
VCO Supply
5 V
5 V
C1
10 nF
5.6 nF
C2
680 nF
120 nF
C3
15 nF
220 pF
C4
1 nF
1 nF
R2
180
Ω
270
Ω
R3
220
Ω
1.2 k
Ω
R4
3.3 k
Ω
1.2 k
Ω
The RF PLL loop filter parameters above are specifically for the VCO listed. If other VCO are used
instead, the values for these parameters will change.
For detailed design and simulation, please check our