iv. Select the SYSREF clock for CLKoutX or CLKoutY with CLKout#_SRC_MUX = 1 (SYSREF) as
desired.
Figure 5-4. Setting Digital Delay, Clock Divider, Analog Delay, and Output Format
4. Depending on the configured output type, the clock output SMAs can be interfaced to a test instrument with
a single-ended, 50-Ω input as follows:
a. For LVDS:
i.
A balun (like ADT2-1T or a high-quality Prodyn BIB-100G) is recommended for differential-to-single-
ended conversion.
b. For LVPECL:
i.
A balun can be used, or
ii. One side of the LVPECL signal can be terminated with a 50-Ω load and the other side can be run
single-ended to the instrument.
c. For HSDS:
i.
A balun (like ADT2-1T or high-quality Prodyn BIB-100G) is recommended for differential-to-single-
ended conversion.
d. For CML:
i.
A balun can be used, or
ii. One side of the CML signal can be terminated with a 50-Ω load and the other side can be run
single-ended to the instrument.
e. For LVCMOS:
i.
Connect the LVCMOS signal to measurement equipment as desired. If an output of a pair is
not used, TI recommends leaving the output floating close to the IC. Alternatively, place a 50-Ω
termination at the end of an unused trace.
5. The phase noise may be measured with a spectrum analyzer or signal source analyzer.
Using TICS Pro to Program the LMK04368-EP
8
LMK04368EPEVM User’s Guide
SNAU283 – OCTOBER 2022
Copyright © 2022 Texas Instruments Incorporated
