2. Connect a reference clock to the CLKin1* port from a signal generator or other source. Use 122.88 MHz for
the default configuration.
3. Connect a USB Cable A Plug to Micro B Plug cable to a PC and the USB connector (J45) at EVM.
4. Program the device with TICS Pro. TICS Pro is available for download at:
http://www.ti.com/tool/ticspro-sw
.
a. Select
LMK04368-EP
from the
Select Device
menu. Click
Select Device → Clock Generator/Jitter
Cleaner (Dual Loop)
.
b. Select
USB2ANY mode
from the
Communication Setup
window. To access this, select
USB
communications → Interface
. Click
Identify
to confirm that the PC to USB communication is working.
A blinking green LED on the USB2ANY indicates the PC is able to communicate through the USB2ANY.
c. Select a default mode from the
Default Configuration
menu. For the quick start, use: CLKin1 122.88
MHz, OSCin 122.88 MHz, VCO1 2949.12 MHz.
d. Press
Ctrl+L
at least once to load all registers. Alternatively, click the
USB communications → Write All
Registers
menu, the
Write All Registers
button on toolbar, or the
Raw Registers
5. Measurements may be made at an active CLKout port through the SMA connector.
2.1.1 Clock Outputs Page Description
Clock outputs are grouped in pairs. This description applies for all clock outputs on the
Clock Outputs
page of
).
1
2
4
20
5
6
7
8
13
14
15
16
17
19
9
11
12
21
22
23
25
24
26
27
18
3
10
Figure 2-2. Clock Outputs Page Description Diagram
1. SYNC_DISX: Prevent the divider from being reset by SYNC/SYSREF path.
2. DCLKX_Y_DIV: Divide value for the device clock. If set to 1, then DCLKX_Y_DCC (DCC & HS) must = 1.
3. DDLYdX_EN: Enable dynamic digital delay for this divider.
4. DCLKX_Y_HSg_PD: If clear, glitchless half-step adjustments are enabled.
5. DCLKX_Y_HS: Set half step for this divider. DCLKX_Y_DCC (DCC & HS) must = 1.
6. DCLKX_Y_DDLY_PD: If clear, the digital delay value is assured when a SYNC occurs.
7. DCLKX_Y_DDLY: The digital delay value to be used when a SYNC occurs.
8. DCLKX_Y_PD: Power down the device clock divider and path.
9. DCLKX_Y_DCC: Enable duty cycle correct and half-step for this device clock divider.
10. DCLKX_Y_POL: If set, polarity of device clock is inverted.
11. DCLKX_Y_BYP: If set, the device clock divider is bypassed for CLKoutX and #15 must be CML.
12. CLKoutX_SRC_MUX: Select device clock or SYSREF clock path for CLKoutX.
13. CLKoutX_Y_IDL: Increase input drive level to improve noise floor at cost of power (approximately 2 mA).
14. SYSREF_GBL_PD: Set the conditional for SCLKX_Y_DIS_MODE registers.
15. CLKoutX_FMT: Set the clock output format for CLKoutX.
16. CLKoutX_Y_ODL: Increase output drive level to improve noise floor at cost of power (approximately 3 mA).
No effect for CLKoutX in bypass mode.
17. CLKoutX_Y_PD: Power down the entire CLKoutX_Y clock pair.
18. SCLKX_Y_DDLY: The SYSREF clock digital delay setting.
Quick Start
SNAU283 – OCTOBER 2022
LMK04368EPEVM User’s Guide
3
Copyright © 2022 Texas Instruments Incorporated
