Description
4
SNOU165A – September 2018 – Revised March 2019
Copyright © 2018–2019, Texas Instruments Incorporated
Using the LMG341xEVM-018 half-bridge and LMG34XX-BB-EVM breakout
board EVM
2
Description
The LMG341xEVM-018 operates as a daughter card as part of a larger custom designed system or with
the LMG34XX-BB-EVM breakout motherboard.
2.1
LMG341xEVM-018
The LMG341xEVM-018 configures two LMG341xR050 GaN FETs in a half bridge. All the bias and level
shifting components are included, allowing low side referenced signals to control both FETs. High
frequency bypass capacitors are included on the power stage in an optimized layout to minimize parasitic
inductance and reduce voltage overshoot.
There are 6 logic pins on the FET card.
Table 1. Logic Pin Function Description
Pin
Description
AGND
Logic and bias power ground return pin. Functionally isolated from PGND.
12V
Auxiliary power input for when the LMG341xEVM-018 is configured in bootstrap mode. Pin is not used
when configured in isolated power mode.
5V
Auxiliary power input for the LMG341xEVM-018. Used to power logic isolators. Used as input bias power
of LMG341xR050 devices when configured in isolated power mode.
FAULT
Logic AND output from FAULT signal from LMG341xR050. Pin is either pulled to AGND or 5V.
Q2 Gate
AGND referenced logic gate signal input for bottom LMG341xR050. Compatible with both 3.3V and 5V
logic.
Q1 Gate
AGND referenced logic gate signal input for top LMG341xR050. Compatible with both 3.3V and 5V logic.
There are 3 power pins on the FET card.
Table 2. Power Pin Function Description
Pin
Description
VSW
Switch node of the half bridge
VDC
Input DC voltage of the half bridge
PGND
Power ground of the half bridge. Functionally isolated from
AGND.
