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High Density EVM Description
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4 SNVU623B – October 2018 – Revised April 2020
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LM5143-Q1 EVM User's Guide
1 High Density EVM Description
The LM5143-Q1EVM-2100 high-density EVM is designed to use a regulated or non-regulated high-voltage
input rail ranging from 5.5 V to 36 V to produce tightly-regulated output voltages of 5 V and 3.3 V at load
currents up to 7 A. Alternatively, as shown in
Figure 2 , a two-phase, 15-A single-output regulator is
configured by changing the MODE, SS1/2, and COMP1/2 switch configurations, and tying the outputs
together. This wide V
IN
range DC/DC solution offers outsized voltage rating and operating margin to
withstand supply rail voltage transients.
The free-running switching frequency is 2.1 MHz and is synchronizable to an external clock signal at a
higher or lower frequency. The power-train passive components selected for this EVM, including buck
inductors and ceramic input and output capacitors, are automotive AEC-Q200 rated and are available from
multiple component vendors.
1.1 Typical Applications
• High-current automotive electronic systems using 2-,3-, and 4-phase implementations
• Dual outputs for ADAS and body electronics
• Infotainment systems and instrument clusters
• Automotive HEV/EV powertrain systems
1.2 Features and Electrical Performance
• Tightly-regulated output voltages of 5 V and 3.3 V with better than ±1% setpoint accuracy
• Wide input voltage operating range of 5.5 V to 36 V
• Single- and dual-output configurations
– Dual outputs of 3.3 V and 5 V rated at 7 A each
– Single output, two-phase solution provides 15 A
• Switching frequency of 2.1 MHz externally synchronizable up or down by 20%
• Ultra-high power conversion efficiency across wide load current ranges
– Full-load efficiency of 90.25% at V
IN
= 12 V (dual outputs of 5 V and 3.3 V at 7 A)
– Full-load efficiency of 91.5% at V
IN
= 12 V (single output of 5 V at 15 A)
• 25-µA controller standby current at V
IN
= 12 V with channel 2 disabled
• Input
π
-stage EMI filter with electrolytic capacitor for parallel damping
– Differential-mode and common-mode filter stages
– Meets CISPR 25 and UNECE Reg 10 EMI standards
• Peak current-mode control architecture provides fast line and load transient response
– Integrated slope compensation adaptive with switching frequency
– Forced PWM (FPWM) or diode emulation mode (DEM) operation
• Integrated high-side and low-side power MOSFET gate drivers
– 3.25-A and 4.25-A sink/source gate drive current capability
– Independent source and sink gate driver pins for adjustable switch (SW) voltage slew rate
– 14-ns adaptive dead-time control reduces power dissipation and MOSFET temperature rise
• Overcurrent protection (OCP) with shunt or inductor DCR current sensing
• Monotonic prebias output voltage start-up
• User-adjustable soft-start time set to 3 ms by 100-nF capacitors connected between SS1/SS2 and
AGND
– Option for output voltage tracking using master track signal connected to SS1 or SS2
• SYNCOUT signal 90° out-of-phase with internal clock
• Power Good indicators for each channel with 100-k
Ω
pullup resistors to VCC
• Selectable forced-PWM (FPWM) or diode emulation (DEM) modes using the MODE pin
• Fully assembled, tested, and proven PCB layout with 100-mm × 75-mm total footprint