Texas Instruments ISO7220 Series, Руководство пользователя

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1.4 The ISO7220x EVM Configuration
INA
OUTB
R8
R4
R6
INB
OUTA
R2
INA
OUTB
R5
R1
OUTA
INB
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Introduction
The ISO7220x EVM configuration has SMA connectors (J1 and J3) set up as the input to the INA (pin 2)
and INB (pin 3) of the ISO7220M in
Figure 1 and Figure 2 . R2 and R8 are 0-
Ω
input series resistors
shown in Figure 4 , and are located next to the J1 and J3 input connectors. R1 and R5 are 50-
Ω
resistors
from each input to ground, and are located on the bottom of the board as shown in Figure 5 .
Figure 4. ISO7220x EVM, Top View
The output channel configuration of the ISO7220x EVM has the OUTA (pin 7) and OUTB (pin 6) of
Figure 1 and Figure 2 connected to SMA connector (J2 and J4) through 0-
Ω
series resistor, R4 and R6 .
Figure 5. ISO7220x EVM, Bottom View
The pads for R3, R7, C1, C12, C13 and C14 are available on the bottom of the EVM for varied loading
conditions if desired by a user.
SLLU098A – June 2007 – Revised July 2009 Dual-Channel Digital Isolator EVM 5
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