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14 SPRUIB9 – December 2016
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DRA72x EVM CPU Board User's Guide
Table 10. SoC Boot Mode Switch Settings (continued)
SoC Interface (Internal System
Boot Input)
CPU Bd Net
DIP Switch Ref Des. Position #
Connections Factory Settings
GPMC_AD14 (sysboot14) GPMC_D14 SW3.P7 OFF
GPMC_AD15 (sysboot15) GPMC_D15 SW3.P8 ON
In addition to the SoC boot settings, the EVM resources must also be set for the desired interface, as
shown in
Table 11 . DIP switch SW5 is used to configure the various EVM memories for boot.
An ON setting selects a logic 0 for the signals, and an OFF setting selects a logic 1. This polarity is
OPPOSITE the SYS_BOOT settings.
(1)
Routing control for GPMC_nCS0 is shared between NOR and NAND flash memories. Ensure that only one DIP switch, SW5.P1 or
SW5.P2, is ever set to the ON state at any one time, so that GMPC_nCS0 is only connected to one memory. Failure to adhere to this
requirement will cause NOR and NAND memory data bus contention.
Table 11. Board Controls for Memory Booting Options
Signals Description DIP Switch Factory Settings I2C1 GPIO Expander
NAND_BOOTn
(1)
Low = Enable GPMC_nCS0 for NAND
flash boot SW5.1 OFF U57.P10
NOR_BOOTn
(1)
Low = Enable GPMC_nCS0 for NOR
flash boot SW5.2 OFF U57.P11
MMC2_BOOT Low = Enable MMC2 Interface for eMMC
flash boot SW5.3 OFF U57.P12
UART_SEL1_3 High = UART3 Interface for UART boot is
enabled. Low = UART1 interface for
terminal SW5.5 ON U57.P14
Table 12. Board Controls for Signaling and Operational Modes
Signals Description DIP Switch Factory Settings I2C1 GPIO Expander
MCASP1_ENn Low = Enable COMx signal paths SW5.6 OFF U57.P15
NOR_ALT_ADDRn
High = Selects default pin location for
GPMC ADDR
Low – Selects alternate/new pin locations
for GPMC
SW5.7 OFF U57.P6
PCI_RESET_SEL
High = PCIe device may reset SoC
Low = SoC may reset the PCIe device
SW5.8 OFF NA
GPMC_WPN Low = Enable write protection of NAND
Flash SW5.9 OFF NA
I2C_EEPROM_WP High = Enable write protection of Board
identification EEPROM SW5.10 OFF NA
3.7 JTAG and Emulator
The JTAG emulation interface is supported through the MIPI 60-pin interfaces. The EVM kit includes an
adapter for supporting other JTAG interfaces, including TI’s 20-pin cJTAG interface. Reset (warm reset)
through the emulator is supported.
The EVM supports up to 20 trace bits. At the SoC and EVM level, the trace pins are muxed with VOUT1
(LCD panel) pins. Thus, these interfaces cannot be used simultaneously. TI recommends any LCD panel
be removed from the system using debug or trace features.