Registers
883
SPRUHI7A – December 2012 – Revised June 2016
Copyright © 2012–2016, Texas Instruments Incorporated
High-Definition Video Processing Subsystem (HDVPSS)
1.3.13.10 VCOMP_reg9 Register (offset = 24h) [reset = 0h]
VCOMP_reg9 is shown in
and described in
Figure 1-559. VCOMP_reg9 Register
31
30
29
28
27
26
25
24
CFG_MAIN_AUX_N_
ONTOP
Reserved
CFG_DSPLY_BCKGRND_CR_VAL
R/W-0h
R-0h
R/W-0h
23
22
21
20
19
18
17
16
CFG_DSPLY_BCKGRND_CR_VAL
CFG_DSPLY_BCKGRND_CB_VAL
R/W-0h
R/W-0h
15
14
13
12
11
10
9
8
CFG_DSPLY_BCKGRND_CB_VAL
CFG_DSPLY_BCKGRND_Y_VAL
R/W-0h
R/W-0h
7
6
5
4
3
2
1
0
CFG_DSPLY_BCKGRND_Y_VAL
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit;
-n
= value after reset
Table 1-476. VCOMP_reg9 Register Field Descriptions
Bit
Field
Type
Reset
Description
31
CFG_MAIN_AUX_N_ONT
OP
R/W
0h
When '1..' the Main window takes precedence over the Aux window
in display areas where they overlap.
When '0..' the Aux window takes precedence over the Main window
in display areas where they overlap.
30
Reserved
R
0h
Reserved
29-20
CFG_DSPLY_BCKGRND
_CR_VAL
R/W
0h
Background Cr/Chroma value for the display output.
19-10
CFG_DSPLY_BCKGRND
_CB_VAL
R/W
0h
Background Cb/Chroma value for the display output.
9-0
CFG_DSPLY_BCKGRND
_Y_VAL
R/W
0h
Background Y/Luma value for the display output.