Texas Instruments DM38x DaVinci, Руководство пользователя

Страница: 351 / 956

www.ti.com
Registers
351 SPRUHI7A – December 2012 – Revised June 2016
Submit Documentation Feedback
Copyright © 2012–2016, Texas Instruments Incorporated
High-Definition Video Processing Subsystem (HDVPSS)
1.3.5 DEI Registers
Table 1-151 lists the memory-mapped registers for the DEI. All register offset addresses not listed in
Table 1-151 should be considered as reserved locations and the register contents should not be modified.
Table 1-151. DEI REGISTERS
Offset Acronym Register Name Section
0h dei_reg0 Frame Size Register Section 1.3.5.1
4h dei_reg1 MDT Filter Bypass Register Section 1.3.5.2
8h dei_reg2 MDT Spatial Frequency Threshold Register Section 1.3.5.3
Ch dei_reg3 EDI Configuration Control Section 1.3.5.4
10h dei_reg4 EDI Lookup Table Register 0 Section 1.3.5.5
14h dei_reg5 EDI Lookup Table Register 1 Section 1.3.5.6
18h dei_reg6 EDI Lookup Table Register 2 Section 1.3.5.7
1Ch dei_reg7 EDI Lookup Table Register 3 Section 1.3.5.8
20h dei_reg8 FMD Window Register 0 Section 1.3.5.9
24h dei_reg9 FMD Window Register 1 Section 1.3.5.10
28h dei_reg10 FMD Control Register 0 Section 1.3.5.11
2Ch dei_reg11 FMD Control Register 0 Section 1.3.5.12
30h dei_reg12 FMD Status Register 0 Section 1.3.5.13
34h dei_reg13 FMD Status Register 1 Section 1.3.5.14
38h dei_reg14 FMD Status Register 2 Section 1.3.5.15