Internal Modules
134
SPRUHI7A – December 2012 – Revised June 2016
Copyright © 2012–2016, Texas Instruments Incorporated
High-Definition Video Processing Subsystem (HDVPSS)
1.2.7.4
Display Timing Generation (DTG)
The DTG (Display Timing Generator) block will generate all the sync and display timing signals for both
OSD interface and DVO interface.
Due to the fast development of display panel technology and lack of the interface standard, the sync
timing for DVO will be designed highly flexible. This will make sure that the device can interface to the
most panels used by digital TV industry; meanwhile, maintains the simplicity for the software
programming.
The details of OSD interface and DVO interface are described in the corresponding sections.
1.2.7.5
DVO (Digital Video Output)
1.2.7.5.1 Output Formats of DVO
lists all formats that the DVO supports.
Table 1-46. DVO Formats
Formats
DVO_D0
DVO_D1
DVO_D2
Single-stream 656
YCbCr
(Unused)
(Unused)
Dual-stream 656
Y
CbCr
(Unused)
Tri-stream 656
Y/G
Cb/B
Cr/R
YUV422 20bit output with
discrete sync
Y
CbCr
(Unused)
30bit output with discrete sync
Y/G
Cb/B
Cr/R
During the two discrete sync modes, following are the sync signals that DVO outputs:
1. DVO_HS
2. DVO_VS
3. DVO_ACTVID
4. DVO_FID
1.2.7.5.2 Embedded Sync Word Definitions of DVO
DVO of the device supports single/dual/tri stream with embedded sync (SAV/EAV).
The active video data in single/dual stream formats are in 4:2:2 YCbCr format.
DVO of the device also supports 10-bit video, the embedded sync SAV/EAV in 10bit format as: 3FF, 000,
000, XXX. All the possible values for XXX are listed in
.
Table 1-47. Definition of SAV and EAV words
BITS
9
8
7
6
5
4
3
2
1
0
SAV/EAV
Hex
Function
1
F
V
H
P3
P2
P1
P0
x
x
0
1
0
0
0
0
0
0
0
0
0
SAV
200
1
1
0
0
1
1
1
0
1
0
0
EAV
276
2
1
0
1
0
1
0
1
1
0
0
SAV
2AC
3
1
0
1
1
0
1
1
0
0
0
EAV
2D8
4
1
1
0
0
0
1
1
1
0
0
SAV
31C
5
1
1
0
1
1
0
1
0
0
0
EAV
368
6
1
1
1
0
1
1
0
0
0
0
SAV
3B0
7
1
1
1
1
0
0
0
1
0
0
EAV
3C4