ADV
ANCEINFORMA
TION
TMS320F28377S, TMS320F28376S, TMS320F28375S, TMS320F28374S
SPRS881A – AUGUST 2014 – REVISED JUNE 2015
5.7
System
5.7.1
Power Sequencing
An external power supply must be used to supply 3.3 V to V
DDIO
, V
DD3VFL
, V
DDOSC
, and V
DDA
and to
provide 1.2 V to V
DD
. The internal VREG is not supported; therefore, the VREGENZ pin must be tied high
to 3.3 V.
The voltage on V
DDIO
should be greater than V
DD
or no less than 0.3 V below V
DD
at all times. V
DDIO
,
V
DD3VFL
, V
DDOSC
, and V
DDA
should be powered up together and be kept within 0.3 V of each other during
operation. Before powering the device, no voltage larger than 0.3 V above V
DDIO
should be applied to any
digital pin, and no voltage larger than 0.3 V above V
DDA
should be applied to any analog pin.
An internal power-on-reset (POR) circuit holds the device in reset and keeps the I/Os in a high-impedance
state during power up. External supply voltage supervisors (SVS) can be used to monitor the voltage on
the 3.3-V and 1.2-V rails and drive XRS low should supplies fall outside operational specifications.
5.7.2
Reset Timing
XRS is the Device Reset (in) and Watchdog Reset (out). The devices have a built-in POR circuit. During a
power-on condition, this pin is driven low by the device. An external circuit may also drive this pin to assert
a device reset.
This pin is also driven low by the MCU when a watchdog reset occurs. During watchdog reset, the XRS
pin is driven low for the watchdog reset duration of 512 OSCCLK cycles.
A resistor between 2.2 k
Ω
and 10 k
Ω
should be placed between XRS and V
DDIO
. A capacitor should be
placed between XRS and V
SS
for noise filtering, it should be 100 nF or smaller. These values will allow the
watchdog to properly drive the XRS pin to V
OL
within 512 OSCCLK cycles when the watchdog reset is
asserted.
Regardless of the source, a device reset causes the device to terminate execution. The program counter
points to the address contained at the location 0x3F FFC0. When reset is deactivated, execution begins at
the location designated by the program counter.
5.7.2.1
Reset Electrical Data and Timing
Table 5-3. Reset (XRS) Timing Requirements
MIN
MAX
UNIT
t
h(boot-mode)
Hold time for boot-mode pins
1.5
ms
t
w(RSL2)
Pulse duration, XRS low on warm reset
3.2
µs
Table 5-4. Reset (XRS) Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
MIN
TYP
MAX
UNIT
Pulse duration, XRS driven low by device after supplies are
t
w(RSL1)
100
µs
stable
t
w(WDRS)
Pulse duration, reset pulse generated by watchdog
512t
c(OSCCLK)
cycles
58
Specifications
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