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ti

12500 TI Boulevard.  Dallas, Texas 75243

Title:

SHEET:

OF:

FILE:

SIZE:

DATE:

REV:

1-Apr-2008 

Drawn By:

Engineer:

Revision History

REV

ECN Number

Approved

DAC8881 Rev A.Sch

DOCUMENTCONTROL #

C1

0.1µF

+5VA

R6

10K

VSS

2

3

6

4

7

1

5

U2

OPA627AU

VCC

C10

1µF

C9

1µF

R12
10K

C12

1nF

W5

R8

0

GND

4

TRIM

5

NC

1

NC

7

NC

8

TEMP

3

OUT

6

V+

2

U3

REF02AU(8)

C11
10µF

C3

0.1µF

VCC

1

3

TP1

TP2

EXTERNAL
REFERENCE

1

2

3

R9
20K

W4

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

J4

OUTPUT HEADER

FS

C5
10µF

DAC8881 EVM

A

J. PARGUIAN

+REFin

1

CLKR

FSR

R3

0

R4

0

-REFin

VOUT

R14
10K

VCC

C7

0.1µF

TP3

VOUT

U2_+IN

U2_-IN

U2_OUT

1

2

3

4

5

6

7

8

9

10

11 12
13 14
15 16
17 18
19 20

J2

Serial Header

TP4

VCC = +15V Analog

AVDD = +2.7V to +5.5V Analog

VSS = 0V to -15V Analog

VCC

1

2

3

4

5

6

7

8

9

10

J6

VSS

+5VA

-5VA

VDD

+3.3VD+1.8VD

+3.3VA

PDN

GPIO1

SCL

SDA

GPIO2

GPIO3
GPIO4

RST

R5 DNP

R7 DNP

R25 DNP

R2

0

SCLK

SDO

W1

+3.3VA

AVDD

W6

R13

100

W12

W3

R1

0

CS

VOUT1

VOUT2

TP5

IOVDD

RFB

RFB1

RFB2

W2

W7

Do not populate
 R5, R7, & R25

W8

3

2

6

7

4

 

8

  U5

OPA277

1

First Proto Release

JLP

J. PARGUIAN

6489897

1

AVDD

5

VREFH

11

RFB

9

VOUT

8

CS

19

SCLK

1

SDI

2

DGND

22

IOVDD

23

AGND

4

GAIN

15

VREFHS

7

VREFL

10

VREFLS

6

TP1

12

TP2

13

RSTSEL

14

USB/BTC

16

RST

17

PDN

18

SDOSEL

20

DVDD

21

SDO

24

LDAC

3

U1

DAC8881

1

2

3

4

5

6

7

8

9

10

11 12
13 14
15 16
17 18
19 20

P2

Serial Header Bottom

C15

0.1µF

IOVDD

C16
10µF

R19
10K

R18
10K

2

3

1

8

4

U4A

OPA2277UA

5

6

7

U4B

OPA2277UA

VCC

VSS

R17
10K

R16
10K

R15
10K

R11
10K

R10
10K

W10

R20

0

TP6
SDO

TP7
SDI

C8

1000pF

C6

2200pF

C13

2200pF

C14

1000pF

C2

0.1µF

R23

50

R26

50

R21

2K

R24
2K

R22
96K

W9

VREFH

1

2

3

4

5

6

J3

CS
SCLK
CLKR
FS
FSR
SDI
DR

DR

LDAC1
LDAC2

LDAC1
LDAC2

RST

GPIO1

SCL

SDA

GPIO2

GPIO3
GPIO4

TP8

dcs
dsclk
dsdi

dsdo

dsdosel

again

avrefhs

avrefls

VREFL

dusb/btc

dldac

1

2

3

4

5

6

7

8

9

11

13

10

12

14

J1

drstsel

C17

0.1µF

C4
0.1µF

W11

+5VA

REF5045ID

A

Production Release

JLP

OPA211

EDGE Numbers:

DAC8881EVM BOM  = 6489895 
DAC8881EVM PWB  = 6489896 
DAC8881EVM DDB (BLOCK)  = 6489897 
DAC8881EVM PCA  = 6489898 
DAC8881EVM KIT (BLOCK)  = 6489899  

Содержание DAC8881

Страница 1: ...Jumper Settings 14 3 6 Schematics 16 4 Using the DAC8881EVM with DXP 16 4 1 Hardware 17 4 2 MMB0 Power Supplies 17 4 3 Software Running DXP 18 4 4 DAC Output Update Options 20 4 5 Data Input Format 2...

Страница 2: ...rint of U3 is compatible with many SO 8 package type reference devices so the user has the flexibility to select the reference supply to set the output range of the DAC8881 other than what is provided...

Страница 3: ...ected Shorting pins 2 and 3 of both jumpers selects the reference voltages that are applied via J4 pins 18 and 20 respectively These voltages normally come from the host platform that is interfaced wi...

Страница 4: ...should include adequate bypassing identifying and managing analog and digital signals and knowing or understanding the mechanical attributes of the components The critical part of the design is the la...

Страница 5: ...s dimensions of 43 1800 mm 1 7000 inch 82 5500 mm 3 2500 inch and the board thickness is 1 5748 mm 0 062 inch Figure 2 through Figure 8 show the individual artwork layers Figure 2 Top Silkscreen Figur...

Страница 6: ...www ti com Figure 4 Layer 2 Ground Plane Figure 5 Layer 3 Power Plane 6 DAC8881 Evaluation Module SLAU257A September 2008 Revised November 2009 Submit Documentation Feedback Copyright 2008 2009 Texas...

Страница 7: ...rformance Figure 6 Layer 4 Bottom Signal Plane Figure 7 Bottom Silkscreen 7 SLAU257A September 2008 Revised November 2009 DAC8881 Evaluation Module Submit Documentation Feedback Copyright 2008 2009 Te...

Страница 8: ...ware The EVM board is tested for all codes of 65535 and the device under test DUT is allowed to settle for 1ms before the meter is read This process is repeated for all codes to generate the measureme...

Страница 9: ...6 10 F 1210 ceramic cap X7R 16V TDK C3225B63X7R1C106Z 4 7 C1 C2 C3 C4 C7 C15 C17 0 1 F 0805 ceramic cap X7R 50V 10 TDK C2012X7R1H104K 5 2 C9 C10 1 F 0805 ceramic cap X7R 16V 10 TDK C3216X7R1C105K 6 2...

Страница 10: ...MMH 102 01 T T 28 10 Shunt 2mm shunt black Samtec 2SN BK G 29 0 R5 R7 R25 2 DNP 30 1 Shunt 0 100 shunt black Samtec SNT 100 BK T 1 P2 P4 and P6 parts are not shown in the schematic diagram All P desig...

Страница 11: ...is connected to the noninverting input of the op amp U2 Figure 10 DAC8881 EVM Default Jumper Configuration 3 2 Host Processor Interface The host processor basically drives the DAC so the DACs proper...

Страница 12: ...nd the signal used depends on the host controller that is selected to communicate with the DAC8881EVM Either signal can be chosen to drive the DAC8881 chip select CS pin The basic function of the CS a...

Страница 13: ...the connector J4 The selected pins of the J4 connector as dictated by the jumper positions of the W2 and W7 jumpers can then be connected to the load to close the loop The EVM includes an external op...

Страница 14: ...e loads Increasing the gain enhances the ability of the amplifier to drive even more capacitance and by adding a load resistor even improves the capacitive load drive capability Table 6 shows the jump...

Страница 15: ...is is the default mode of the EVM from the factory Routes the reference feedback RFB pin of the DAC8881 to J4 pin 8 to provide the option to close the output op amp U2 loop as close as possible to the...

Страница 16: ...wn status If jumper is installed on pins 13 and 14 the SDOSEL pin of the DAC8881 is tied to ground so that the DAC device can be operated in daisy chain mode DAC8881 IOVDD is powered with 5VD J3 DAC88...

Страница 17: ...3 100 W12 W3 R1 0 CS VOUT1 VOUT2 TP5 IOVDD RFB RFB1 RFB2 W2 W7 Do not populate R5 R7 R25 W8 3 2 6 7 4 8 U5 OPA277 1 First Proto Release JLP J PARGUIAN 6489897 1 AVDD 5 VREFH 11 RFB 9 VOUT 8 CS 19 SCLK...

Страница 18: ...O NOT connect the MMB0 to your PC before installing the DXP software as described in the DXP User s Guide Installing the software will ensure the necessary drivers are properly loaded to run the hardw...

Страница 19: ...MMB0 Connect all other analog supplies as necessary to J14 on the MMB0 4 3 Software Running DXP Install DXP on a laptop or personal computer running Windows XP as per the detailed instruction in the...

Страница 20: ...lease ensure no jumpers are placed on J1 pins 9 10 When the RST pin is low the device is in hardware reset mode and the input register and DAC latch are set to the value defined by the RSTSEL pin refe...

Страница 21: ...1 2 routes the LDAC input to pin 15 of J2 This feature allows the user to Timer apply an LDAC input from an external source In this mode J2 pin 15 provides an interrupt to the DSP on the MMB0 which tr...

Страница 22: ...terature Number DAC8881 SBAS422 REF02 SBVS003 REF5050 SBOS410 REF5045 SBOS410 OPA211 SBVS058 OPA627 SBOS165 OPA277 SBOS079 OPA2277 SBOS079 OPA227 SBOS110 5 2 Questions About This or Other Data Convert...

Страница 23: ...oduct This notice contains important safety information about temperatures and voltages For additional information on TI s environmental and or safety programs please contact the TI application engine...

Страница 24: ...ce TI is not responsible or liable for any such statements TI products are not authorized for use in safety critical applications such as life support where a failure of the TI product would reasonabl...

Страница 25: ...Mouser Electronics Authorized Distributor Click to View Pricing Inventory Delivery Lifecycle Information Texas Instruments DAC8881EVM...

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