Digital Interface
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The analog interface is populated on both the top and the bottom sides of the evaluation board. All of the
output pins of the DACx562 are routed directly to the J1 connector.
The GND pins of the DACx562 are connected directly to the ground of the evaluation board.
The DAC8562EVM is designed to allow the user to choose from using the DACx562 internal reference,
the onboard 2.5V REF5025, or a user-supplied external reference source for the DAC. Depending on how
the DACx562 is configured, pin J1.20 is either an input or an output. If the DACx562 internal reference is
used, then J1.20 is the output of the V
REFIN
/V
REFOUT
pin on the DAC. If an external reference is used, other
than the onboard REF5025, J1.20 is used to provide the external reference voltage.
Additionally, the evaluation board contains an
OPA379
in a buffer configuration to condition the internal
reference if the user would like to use the signal to drive another component. The buffered signal is routed
to pin J1.15.
If the DACx562 bipolar circuit is installed on the EVM, the output of the installed operational amplifier is
routed to pin J1.10 on the J1 connector.
3
Digital Interface
3.1
Serial Peripheral Interface
Samtec part numbers SSW-110-22-F-D-VS-K and TSM-110-01-T-DV-P provide a 10-pin, dual-row,
header/socket combination at J2. This header/socket provides access to the digital control data pins from
both J2A (top side) and J2B (bottom side) of the connector. Consult Samtec at
http://www.samtec.com
or
call 1-800-SAMTEC-9 for a variety of mating connector options.
Table 2
describes the serial interface
pins.
Table 2. J2.3: Serial Interface Pins
Pin No.
Signal Name
I/O Type
Pull-Up
Function
J2.1
SYNC0
In
None
DACx562 SYNC signal. Jumper
JP5 determines SYNC pin
J2.3
SCLK
In
None
DACx562 SCLK signal
J2.5
SCLK
In
None
DACx562 SCLK signal
J2.7
SYNC1
In
None
DACx562 SYNC signal. Jumper
JP5 determines SYNC pin
J2.9
SYNC2
In
None
DACx562 SYNC signal. Jumper
JP5 determines SYNC pin
J2.11
SDI
In
None
DACx562 DIN signal
J2.15
LDAC1
In
High
DACx562 LDAC signal. Jumper
JP6 determines LDAC control pin
J2.17
LDAC2
In
High
DACx562 LDAC signal. Jumper
JP6 determines LDAC control pin
J2.19
CLR
In
High
DACx562 CLR signal.
J2.2
Unused
—
—
—
J2.6 to J2.8 (even)
Unused
—
—
—
J2.12 to J2.16 (even)
Unused
—
—
—
J2.20
Unused
—
—
—
J2.4, J2.10, J2.18
GND
In/Out
None
Ground
The DACx562 is controlled through a serial peripheral interface using the pins available on the J2 header.
The four SPI signals are connected to the DAC I/O signals through 33
Ω
series resistors. The SYNC signal
can be routed to one of three pins on the J2 header: J2.1, or J2.7 and J2.9. The SCLK signal is routed to
both J2.3 and J2.5. The DIN signal is routed to the J2.11 pin on the J2 header.
4
DAC7562EVM, DAC8562EVM
SBAU183A
–
May 2011
–
Revised June 2011
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2011, Texas Instruments Incorporated
