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DAC5687 EVM Operational Procedure
⋅
Sync_NCO:
When set, the NCO phase accumulator is cleared with a phstr low to high
transition.
⋅
Phstr Clk Div Selects the clock used to latch the PHSTR input when restarting the
Select:
internal clock dividers. When set, the full rate CLK2 signal latches PHSTR.
When cleared, the divided down input clock signal latches PHSTR.
⋅
DAC Serial
When set, both DAC A and DAC B input data is replaced with fixed data
Data:
loaded into the 16 bit serial interface DAC Static Data.
o
Counter Mode: Controls the internal counter that can be used as the DAC
data source. See the data sheet for more information.
o
DAC Static Data: When DAC Serial Data is set, both DAC A and DAC B
input data is replaced with fixed data loaded with this value. Range = 0 to
65535.
⋅
NCO:
When set, enables NCO.
o
NCO Gain: Sets NCO gain resulting in a 2x increase in NCO output
amplitude. Except for F
S
/2 and F
S
/4 mixing NCO frequencies, this
selection can result in saturation for full scale inputs. Consider using QMC
gain for lower gains.
⋅
QMC:
When set, enables the QMC.
o
QMCA Gain: Sets QMC gain A to a range = 0 to 2047. See the data
sheet for more information.
o
QMC B Gain: Sets QMC gain B to a range = 0 to 2047. See the data
sheet for more information.
o
QMC Phase: Sets QMC phase to a range = -512 to 511. See the data
sheet for more information.
⋅
Mode:
Used to select the coarse mixer mode. See the DAC5687 data sheet for
more information.
⋅
PLL Divider:
Sets VCO divider to div by 1, 2, 4, or 8.
⋅
Interpolation: Sets FIR Interpolation factor: {X2, X4, X4L, X8}. X4 uses lower power than
4xL, but F
DAC
= 320 MSPS max when NCO or QMC are used.
⋅
Phstr Init.
Adjusts the initial phase of the F
S
/2 and F
S
/4 cmix block at PHSTR.
Phase:
⋅
Sync FIFO:
Sync source selection mode for the FIFO. When a low to high transition is
detected on the selected sync source, the FIFO input and output pointers
are initialized. See the DAC5687 data sheet for source description.
⋅
Alt.
Sets PLLLOCK output pin to F
DAC
frequency when operating in the PLL
PLLLOCK
mode. Settings must be used in conjunction with the interpolation setting
Output:
to achieved desired rate (i.e. set to F
DAC
/2 for 2x interpolation, set to
F
DAC
/4 for 4x interpolation). Note, there is no option for the 8x mode. The
jumper at W1 (EXTLO) must be removed to utilize this functionality.
SLWU017B – APRIL 2005 – Revised March 2007
DAC5687 EVM
15
