Texas Instruments DAC5652, Руководство пользователя

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Schematic Diagram
2-2
2.1 Schematic Diagram
The schematic diagram for the EVM is attached at the end of this document.
2.2 Circuit Function
The following paragraphs describe the EVM circuits.
2.2.1 Input Clock
The DAC5672/62/52 EVM default operation setting is with a single-ended
input clock sent to the DAC5672/62/52. A 3 V
p-p
, 1.5-V offset, 50% duty cycle
external square wave is applied to SMA connector J3. This input represents
a 50-
Ω
load to the source. In order to preserve the specified performance of
the DAC5672/62/52 converter, the clock source should feature very low jitter.
Using a clock with a 50% duty cycle will give optimum dynamic performance.
Options are provided to operate the two DAC’s with separate clocks. Another
option allows the user to provide separate write enables when using interleave
mode. See Table 2−1 for proper board configuration.
2.2.2 Input Data
The DAC5672/62/52 EVM can 3.3-V CMOS logic level data inputs
through the 34-pin headers J9 and J10 per Table 2−1 and Table 2−2. The user
can provide series dampening resistors to minimize digital ringing and
switching noise if required. The default values are 0
Ω
. An option is also
available to provided pulldown resistors to the input data paths. Before using
the pulldown resistors, the user must make sure the source providing the input
data can drive the load the pulldown resistors adds to the data path.
Table 2−1. Input Connector J1
J9 Pin No. Description J9 Pin No. Description
1 Port 1 Data Bit 13 (MSB) 18 GND
2 GND 19 Port 1 Data Bit 4
3 Port 1 Data Bit 12 20 GND
4 GND 21 Port 1 Data Bit 3
5 Port 1 Data Bit 11 22 GND
6 GND 23 Port 1 Data Bit 2
7 Port 1 Data Bit 10 24 GND
8 GND 25 Port 1 Data Bit 1
9 Port 1 Data Bit 9 26 GND
10 GND 27 Port 1 Data Bit 0
11 Port 1 Data Bit 8 28 GND
12 GND 29
13 Port 1 Data Bit 7 30 GND
14 GND 31
15 Port 1 Data Bit 6 32 GND
16 GND 33
17 Port 1 Data Bit 5 34 GND