Texas Instruments DAC12DL3200, Руководство пользователя, Страница: 2 / 32

Figure 3-9. IO Delay Register Write........................................................................................................................................... 15
Figure 3-10. DAC Channel A Output......................................................................................................................................... 16
Figure 4-1. 2nd Nyquist Zone Testing........................................................................................................................................ 17
Figure 4-2. DACA Tab With NCO settings................................................................................................................................. 19
Figure 4-3. NCOA Calculation................................................................................................................................................... 20
Figure 5-1. Register Log file...................................................................................................................................................... 21
Figure 6-1. Configuration GUI: Low-Level View Tab.................................................................................................................. 22
Figure B-1. Onboard Clocking Setup......................................................................................................................................... 25
Figure B-2. Default Board Clock Configuration Circuit (External Clock Mode).......................................................................... 26
List of Tables
Table 6-1. Low-Level Controls................................................................................................................................................... 23
Table A-1. Troubleshooting........................................................................................................................................................ 24
Trademarks
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Rohde & Schwarz ® are registered trademarks of Rohde & Schwarz GmbH & Co.
All trademarks are the property of their respective owners.
1 Introduction
The DAC12DL3200 is a very low latency, dual-channel, 12-bit RF sampling digital-to-analog converter (DAC),
capable of operating at sampling rates up to 3.2 Giga-samples per second (GSPS) in dual-channel mode,
or 6.4 GSPS in single-channel mode. The DAC can transmit signal bandwidths beyond 2 GHz at carrier
frequencies approaching 8 GHz when using multi-Nyquist output modes. The DAC12DL3200EVM device input
data is transmitted over a high-speed LVDS interface. This evaluation board also includes the following important
features:
• Transformer-coupled output allowing for a single-ended 50-Ω output signal up to 8 GHz
• The LMX2592 clock synthesizer as an option to generate the DAC sampling clock
• Transformer-coupled input clock option (board default setup) for quick setup with external clock sources
• LMK04828 clock synthesizer for DAC SYSREF and FPGA reference clock source
• Device register programming through USB connector and FTDI USB-to-SPI bus translator
• High-speed LVDS data input over a 400-pin FMC interface connector
Figure 1-1. DAC12DL3200EVM
The TI TSW14DL3200EVM pattern generator, when used with the TI High-Speed-Data-Converter (HSDC) Pro
Software GUI, is used to send LVDS data test patterns to the DAC12DL3200EVM.
With proper hardware selection in the HSDC Pro software, the TSW14DL3200EVM is automatically configured
to support the different modes of operation of the DAC12DL3200. The interface provides LVDS output data up to
1600 MSPS.
Trademarks www.ti.com
2 DAC12DL3200 Evaluation Module SBAU374 – MAY 2021
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