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B DAC12DL3200EVM Onboard Clocking Configuration
This appendix provides settings for modifying the EVM for onboard clocking mode. In this mode, no external
clocks are required. The LMK04828 uses the onboard 100-MHz VCXO and the internal PLL2 to provide the
required clocks along with the LMX2592.
The DAC12DL3200EVM GUI provides 12 configuration files to be used with this mode. The following list
describes a few of them:
1. LMK_100M_LMX_6400M_Mode2_NRZ_Single_DAC.cfg : Operates the DAC in mode 2 with a sample rate
of 6.4 GHz.
2. LMK_100M_LMX_3200M_Mode0_NRZ_Dual_DAC.cfg : Operates the DAC in mode 0 with a sample rate of
3.2 GHz.
3. LMK_100M_LMX_1600M_Mode1_NRZ_Dual_DAC.cfg : Operates the DAC in mode 1 with a sample rate of
1.6 GHz.
4. LMK_100M_LMX_6400M_Mode0_2xRF_Dual_DAC.cfg : Operates the DAC in mode 0 with a sample rate
of 6.4 GHz.
5. LMK_100M_LMX_6400M_NCOA_1_4_100_400MHz.cfg : Operates the DAC in NCO mode with CHA output
options of 100 MHz, 200 MHz, 300 MHz, and 400 MHz.
When using the "LMK_100M_LMX_6400M_Mode2_NRZ_Single_DAC.cfg" configuration file, the LMK04828
provides a 100-MHz reference clock to the LMX2592, a 50-MHz SYSREF clock to the DAC and a 400-MHz
reference clock to the FPGA on the TSW14DL3200EVM.
The LMX2592 uses a 100-MHz reference clock from the LMK04828 and an internal PLL to provide the 6.4-GHz
clock to the DAC. All clocks are synchronized to the 100-MHz VCXO.
To configure the DAC12DL3200EVM to use onboard clock mode, complete the following steps:
1. Remove C7 and C6, and populate C277 and C278.
2. Install FB28 with MuRata BLM18AG121TN1D or equivalent. This is located on the bottom of the board under
Y2.
3. Remove the shunt on the LMX_CE jumper J6.
Figure B-1. Onboard Clocking Setup
4. Remove the signal generators.
5. Program the DAC using the DAC12DL3200 GUI.
a. Press the DAC RESET switch on the EVM.
b. In the DAC GUI
Low Level View tab, select the configuration file called
"LMK_100M_LMX_6400M_Mode2_NRZ_Single_DAC.cfg".
6. Send a test pattern using HSDC Pro GUI.
www.ti.com DAC12DL3200EVM Onboard Clocking Configuration
SBAU374 – MAY 2021
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DAC12DL3200 Evaluation Module 25
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