Electrical Characteristics
(Continued)
Tested at V
CC
= 4.75 V
DC
and 15.75 V
DC
, T
A
=25˚C, V
REF
=10.000 V
DC
unless otherwise noted
Parameter
Conditions
See
Note
V
CC
=12V
DC
±
5%
V
CC
=5V
DC
±
5%
to 15V
DC
±
5%
Units
Min.
Typ.
Max.
Min.
Typ.
Max.
Output
I
OUT1
All data inputs
60
60
pF
Capacitance I
OUT2
latched low
250
250
pF
I
OUT1
All data inputs
250
250
pF
I
OUT2
latched high
60
60
pF
Supply Current
Drain
T
MIN
≤
T
A
≤
T
MAX
6
0.5
3.5
0.5
3.5
mA
Output Leakage
T
MIN
≤
T
A
≤
T
MAX
6
Current
I
OUT1
All data inputs
latched low
10
200
200
nA
I
OUT2
All data inputs
latched high
200
200
nA
Digital Input
T
MIN
≤
T
A
≤
T
MAX
6
Voltages
Low level
LCN and LCWM suffix
0.8, 0.8
0.7, 0.8
V
DC
High level (all parts)
2.0
2.0
V
DC
Digital Input
T
MIN
≤
T
A
≤
T
MAX
6
Currents
Digital inputs
<
0.8V
−40
−150
−40
−150
µA
DC
Digital inputs
>
2.0V
1.0
+10
1.0
+10
µA
DC
Current
t
S
V
IL
= 0V, V
IH
= 5V
500
500
ns
Settling Time
Write and
t
W
V
IL
=0V, V
IH
=5V,
XFER Pulse
T
A
= 25˚C
8
150
60
320
200
ns
Width
T
MIN
≤
T
A
≤
T
MAX
9
320
100
500
250
ns
Data Set Up
t
DS
V
IL
= 0V, V
IH
= 5V,
Time
T
A
=25˚C
9
150
80
320
170
ns
T
MIN
≤
T
A
≤
T
MAX
320
120
500
250
ns
Data Hold
t
DH
V
IL
=OV, V
IH
=5V
Time
T
A
=25˚C
9
200
100
320
220
ns
T
MIN
≤
T
A
≤
T
MAX
250
120
500
320
ns
Control Set
t
CS
V
IL
=0V, V
IL
=5V,
Up Time
T
A
=25˚C
9
150
60
320
180
ns
T
MIN
≤
T
A
≤
T
MAX
320
100
500
260
ns
Control Hold
t
CH
V
IL
=0V, V
IH
=5V,
Time
T
A
=25˚C
9
10
0
10
0
ns
T
MIN
≤
T
A
≤
T
MAX
10
0
10
0
ns
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating
the device beyond its specified operating conditions.
Note 2: All voltages are measured with respect to GND, unless otherwise specified.
Note 3: This 500 mW specification applies for all packages. The low intrinsic power dissipation of this part (and the fact that there is no way to significantly modify
the power dissipation) removes concern for heat sinking.
Note 4: For current switching applications, both I
OUT1
and I
OUT2
must go to ground or the “Virtual Ground” of an operational amplifier. The linearity error is degraded
by approximately V
OS
÷V
REF
. For example, if V
REF
=10V then a 1 mV offset, V
OS
, on I
OUT1
or I
OUT2
will introduce an additional 0.01% linearity error.
Note 5: Guaranteed at V
REF
=
±
10 V
DC
and V
REF
=
±
1 V
DC
.
Note 6: T
MIN
=0˚C and T
MAX
=70˚C for “LCN” and “LCWM” suffix parts.
Note 7: The unit “FSR” stands for “Full Scale Range.” “Linearity Error” and “Power Supply Rejection” specs are based on this unit to eliminate dependence on a par-
ticular V
REF
value and to indicate the true performance of the part. The “Linearity Error” specification of the DAC1006 is “0.05% of FSR (MAX).” This guarantees that
after performing a zero and full scale adjustment (See Sections 2.5 and 2.6), the plot of the 1024 analog voltage outputs will each be within 0.05%xV
REF
of a straight
line which passes through zero and full scale.
Note 8: This specification implies that all parts are guaranteed to operate with a write pulse or transfer pulse width (t
W
) of 320 ns. A typical part will operate with t
W
of only 100 ns. The entire write pulse must occur within the valid data interval for the specified t
W
, t
DS
, t
DH
, and t
S
to apply.
Note 9: Guaranteed by design but not tested.
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3
PrintDate=1998/11/17 PrintTime=11:38:08 46711 ds005688 Rev. No. 4
cmserv
Proof
3
