Configuring the Board
Reset or Supply Control Pin (RESETN_PWR): This pin has dual functions, depending on the mode
selection. This pin acts as a RESETN pin in Interface-programming mode or controls the device core and
output supply voltage setting. Button SW6 and RESET_PWR header are dedicated for this pin. This pin
has an internal 50-k
Ω
pull-up resistor. In Interface-programming mode, the header (RESET_PWR) is left
open or connects the jumper to DVDD. Connecting the jumper to GND or pressing the button (SW6) puts
the device in reset mode. In Pin mode, set the jumper to GND for a 1.8-V power supply and to DVDD for a
2.5-V/3.3-V power supply.
Reference Select Pin (REF_SEL): This pin has an internal 50-k
Ω
pull-up resistor. Connect the header
REF_SEL to GND for PRI_REF input and leave open or connect to DVDD for SEC_REF input selection.
See Table 34 in the data sheet (
) for a detailed description.
Status Pin (STATUS1/PIN0): Depending on the operation mode, this is either an input or output pin. In
Interface-programming mode, this pin (header STATUS1_PIN0) provides the indication of a particular
reference clock selection to the PLL or PLL lock and/or unlock or loss of references depending on
Register 3 Bit 10-12 settings. See
for a full description:
Table 3. STATUS1 Functional Description
Status Signal
Signal Type
Register Bit
Description
Name
SEL_REF
LVCMOS
R3.12
Indicates reference selected for PLL:
“0”
→
Primary
“1”
→
Secondary
LOSS_REF
LVCMOS
R3.11
Loss of reference input observed at input, Smart MUX output in observation
window for PLL:
“0”
→
Reference input present
“1”
→
Loss of reference inputs
PLL_UNLOCK
LVCMOS
R3.10
Indicates unlock status for PLL:
“0”
→
PLL locked
“1”
→
PLL unlocked
In pin mode, this becomes an input pin and the header pin, STATUS1_PIN0, is controlled by PIN0 which
connects to GND or DVDD.
Device Control Pins (SDI/SDA/PIN1, SDO/AD0/PIN2, SCS/AD1/PIN3 and SCL/PIN4): These four pins
have multiple functions depending on the device’s programming interface (SPI or I
2
C) and pin-control
modes. See the data sheet (
) for detailed descriptions and see
for jumper
connections.
Table 4. Device Control Pin Functions
Programming
Header
Header
Header
Header
Remarks
Mode
SDI_SDA_PIN1
SDO_AD0_PIN2
SCS_ADI_PIN3
SCL_PIN4
SPI
Open
Open
Open
Open
Jumpers must not be connected in this mode
Open
GND
(1)
GND
(1)
Open
Header SDO_ADO_PIN2 and SCS_ADI_PIN3
I
2
C
provide the I
2
C address option
Pin Mode
DVDD or GND
DVDD or GND
DVDD or GND
DVDD or GND
The pin selections determine the predefined device’s
functional condition
(1)
The control software assumes the default address bit settings for AD[1:0] is 00.
7.5
Selecting the Loop Filter
The CDCM6208 includes an on-chip PLL with a partially-integrated loop filter. External loop components
(C1, C2 and R2) are required to complete the PLL. The external loop filter is chosen by selecting one from
the four available options on the CDCM6208EVM using the dip switch, SW5. Depending upon the device’s
operation mode, synthesizer or jitter cleaning, selecting appropriate loop filter values is critical. Two loop
filters, 1 and 2, are for synthesizer mode and the other two filters, 3 and 4, are for jitter cleaning mode. If
different RC components are required based on the customer’s PLL configuration, these components
must be replaced by appropriate resistor and capacitors.
9
SCAU049 – May 2012
CDCM6208 Evaluation Board
Copyright © 2012, Texas Instruments Incorporated
