Configuring the Board
7.3
Configuring the Reference Inputs
The CDCM62008 offers two inputs (PRI_REF and SEC_REF). SMA J18 and J19 are dedicated for
PRI_REF (IN1p and IN1n) and SMA J20 and J21 are dedicated for SEC_REF (1N2p and 1N2n). Both
inputs in the EVM are AC-coupled, by default, using coupling capacitors (C25 and C26 for PRI_REF and
C29 and C30 for SEC_REF). CDCM6208 does NOT have any internal termination or biasing; so, external
biasing is required after AC coupling. Headers JMP10 and JPM11 provide the options for PRI_REF input
biasing and SEC_REF input biasing, respectively. Depending on the input signaling level and power
supply selection, proper biasing must be selected, see
.
Table 1. Input Selection Jumper Settings
Input Signaling Level
Input Supply Voltage
JPM10 and JPM11 Selection
CML
1.8 V/2.5 V/3.3 V
DVDD
LVDS
2.5 V/3.3 V
1P2V
LVDS
1.8 V
0P9V
LVCMOS
1.8 V/2.5 V/3.3 V
GND
(1)
Disabled
N.A.
None
(1)
This 50
Ω
to GND is only required if a signal generator is used.
R83, R84, R85, and R86 resistors (49.9
Ω
) provide the termination for 50-
Ω
trace.
Place 0-
Ω
resistors in R87 and R89 and remove R72 and R73 resistors for the external clock to SEC_REF
connection.
LVCMOS inputs are single ended and only the positive pins (IN1p for PRI_REF and IN2p for SEC_REF)
of the inputs are used and DC terminations are recommended. Replace C25 with a 0-
Ω
resistor for
PRI_REF and C29 with a 0-
Ω
resistor for SEC_REF.
SEC_REF accepts crystal input. SEC_REF input is configured for crystal input by default and a 25-MHz
crystal is placed in Y1. C27 and C28 provide the load capacitance options for the crystal.
7.4
Configuring the Control Pins
The device has multiple dedicated pins controlling and configuring the operation. These pins must be set
as instructed for correct device operation.
Power Down Pin (PDN): This pin has an internal 50-k
Ω
pull-up resistor. For normal operation, the PDN
pin should be left open or connect the jumper (header PDN) to DVDD. For power-down mode, connect the
jumper to GND.
Synchronization Pin (SYNCN): This pin has an internal 50-k
Ω
pull-up resistor. For normal operation, the
SYNCN pin should be left open or connect the jumper (header SYNC) to DVDD. An external signal uses
this header to synchronize the outputs. In addition to the header, button SW7 toggles the SYNCN pin.
Mode Selection Pins (SI_MODE0 and SI_MODE1): These two pins select the mode of device
configuration. The SI_MODE1 pin has an internal pull-up resistor and the SI_MODE0 pin has an internal
pull-down resistor. The jumpers on the header, SI_MODE0 and SI_MODE1, must be set as shown in
.
Table 2. Mode Selection Jumper Settings
Jumper On SI_MODE1 Header
Jumper On SI_MODE0 Header
Mode of Configuration
GND
Open or GND
SPI mode
GND
DVDD
I
2
C mode
Open or DVDD
Open or GND
Pin mode
8
CDCM6208 Evaluation Board
SCAU049 – May 2012
Copyright © 2012, Texas Instruments Incorporated
