Control Panel Demonstration
First column is a comment. Second column is the combined device-address and register-address. Third
column is the register value. Last column is the CRC.
5.19 I2C
The I2C section shows the I2C Base Address of the bq76925 and the group address. These are 0x20 and
0x04, respectively. The base address is the group address shifted to the left by three places.
The user can use this I2C section to read and write data to the bq76925.
5.20 I2C Register Read
To read a register, select the desired register to read using the drop-down box. Refer to the product data
sheet to understand the meaning and usage of each register. Then click the Read button. The result is
displayed in the Monitor window.
For example, a read of register 0x01, CELL_CTL, appear as:
I2C_R:
SPACER
22
SPACER
00
SPACER
1A.
The first number, 0x22, is the combined device address and the register number. The second number,
0x00, is the value of the register. The third number, 0x1A, is the CRC. If the CRC_EN bit in the
CONFIG_2 register is not set, the CRC value 0x1A does not appear.
5.21 I2C Register Write
To write a register, select the desired register to write using the drop-down box. See the product data
sheet to understand the meaning and usage of each register. Enter the value to be written in hexadecimal
notation. Then click the Write button. The result is displayed in the Monitor window.
If the Update GUI on write checkbox is selected, then the change to the register is updated in the Volatile
Control Registers section.
5.22 I2C Communications With MSP430F2122
The I2C device address of the MSP430F2122 was assigned as 0x40 so as to not interfere with the
address structure of the bq76925.
The MSP430 reads the various analog outputs of the bq76925 and stores the results, in terms of counts,
in registers in its memory. The MSP430 A/D converter has 10 bits of resolution. The software accesses
these registers. The register map inside the MSP430 is shown in
Table 19. Data From MSP430F2122
Byte
Name
Description
Units
Number
Status of Alert pin. Bit zero indicates level
1
Status
of Alert pin:
None
1=High, 0=Low (Overcurrent).
2
Reserved
Reserved
None
29
SLUU514
–
July 2011
bq76925EVM Evaluation Module
Copyright
©
2011, Texas Instruments Incorporated
