9.3.17 Thermal Protection
During the charging process, to prevent overheating in the device, the junction temperature of the die, T
J
, is
monitored. When T
J
reaches T
(SHUTDOWN)
the device stops charging, disables the PMID output, disables the
SYS output, and disables the LS/LDO output. During the time that T
(SHUTDOWN)
is exceeded, the safety timer is
reset . The charge cycle resumes when T
J
falls below T
(SHUTDOWN)
by T
(HYS)
.
To avoid reaching thermal shutdown, ensure that the system power dissipation is under the limits of the device.
The power dissipated by the device can be calculated using
.
P
DISS
= P
(BLOCK)
+ P
(SYS)
+ P
(LS/LDO)
+ P
(BAT)
(5)
Where
• P
(BLOCK)
= (V
IN
– V
(PMID)
) x I
IN
• P
(SYS)
= I
SYS
2
x R
DS(ON_HS)
• P
(LS/LDO)
= (V
(INLS)
– V
(LS/LDO)
) x I
(LS/LDO)
• P
(BAT)
= (V
(PMID)
– V
(BAT)
) x I
(BAT)
9.3.18 Typical Application Power Dissipation
The die junction temperature, T
J
, can be estimated based on the expected board performance using
.
T
J
= T
A
+ θ
JA
x P
DISS
(6)
The θ
JA
is largely driven by the board layout. For more information about traditional and new thermal metrics,
see the IC Package Thermal Metrics application report
. Under typical conditions, the time spent in this
state is short.
9.3.19 Status Indicators ( PG and INT)
The device contains two open-drain outputs that signal its status and are valid only after the device has
completed start-up into a valid state. If the part starts into a fault, interrupts will not be sent. The PG output
signals when a valid input source is connected. PG pulls to GND when V
IN
> V
UVLO,
V
IN
> V
BAT
+V
SLP
and V
IN
<
V
OVP
. PG is high-impedance when the input power is not within specified limits. Connect PG to the desired logic
voltage rail using a 1-kΩ to 100-kΩ resistor, or use with an LED for visual indication.
The PG pin can be configured as a MR shifted (MRS) output when the PGB_MRS bit is set to 1. PG is high-
impedance when the MR input is not low, and PG pulls to GND when the MR input is below V
OL(TH_MRS)
.
Connect PG to the desired logic voltage rail using a 1-kΩ to 100-kΩ resistor.
The INT pin is pulled low during charging when the EN_INT bit is set to 1 and interrupts are pulled high. When
EN_INT is set to 0, charging status is not indicated on the INT pin. When charge is complete or disabled, INT is
high impedance. The charge status is valid whether it is the first charge or recharge. When a fault occurs, a 128
µs pulse (interrupt) is sent on INT to notify the host.
9.3.20 Chip Disable ( CD)
The device contains a CD input that is used to disable the device and place it into a high impedance mode when
only battery is present. In this case, when CD is low, PMID and SYS remain active, and the battery discharge
FET is turned on. If the LS/LDO output has been enabled prior to pulling CD low, it will stay on. The LSCTRL pin
can also enable/disable the LS/LDO output when the CD pin is pulled low. The CD pin has an internal pull-down.
If V
IN
is present and the CD input is pulled low, charge is enabled and all other functions remain active. If V
IN
is
present and the CD input is pulled high, charge is disabled.
9.3.21 Buck (PWM) Output
The device integrates a low quiescent current switching regulator with DCS control allowing high efficiency down
to 10-µA load currents. DCS control combines the advantages of hysteretic and voltage mode control. The
internally compensated regulation network achieves fast and stable operation with small external components
and low ESR capacitors. During PWM mode, it operates in continuous conduction mode, with a frequency up to
SLUSDA7A – APRIL 2018 – REVISED JANUARY 2021
26
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