PCB Layout Guideline
3
PCB Layout Guideline
Minimize the switching node rise and fall times for minimum switching loss. Proper layout of the
components minimizing high-frequency current path loop is important to prevent electrical and magnetic
field radiation and high frequency resonant problems. This PCB layout priority list must be followed in the
order presented for proper layout:
1. Place the input capacitor as close as possible to the PMID and GND pin connections and use the
shortest possible copper trace connection or GND plane.
2. Place the inductor input terminal as close to the SW pin as possible. Minimize the copper area of this
trace to lower electrical and magnetic field radiation but make the trace wide enough to carry the
charging current. Do not use multiple layers in parallel for this connection. Minimize parasitic
capacitance from this area to any other trace or plane.
3. Put an output capacitor near to the inductor and the IC. Tie ground connections to the IC ground with a
short copper trace connection or GND plane.
4. Route analog ground separately from power ground. Connect analog ground and connect power
ground separately. Connect analog ground and power ground together using power pad as the single
ground connection point or use a 0-
Ω
resistor to tie analog ground to power ground.
5. Use a single ground connection to tie the charger power ground to the charger analog ground just
beneath the IC. Use ground copper pour but avoid power pins to reduce inductive and capacitive noise
coupling.
6. Place decoupling capacitors next to the IC pins and make the trace connection as short as possible.
7. It is critical that the exposed power pad on the backside of the IC package be soldered to the PCB
ground. Ensure that there are sufficient thermal vias directly under the IC, connecting to the ground
plane on the other layers.
8. The via size and number should be enough for a given current path.
See the EVM design for the recommended component placement with trace and via locations. For the
QFN information, refer to
and
.
4
PCB Thermal Design
The IC is one of the major heat dissipation components on the EVM, and is cooled with thermal
PowerPAD vias connected to the bottom layer. The copper pour on the bottom layer is 1 in x 2 in
representing a thermal design of this size. Note how there are very few routing etches in the bottom layer
and that they are positioned to maximize (not impede) the flow of heat away from the IC. All good thermal
designs have at least one layer of 2-oz copper (without cuts) to spread the heat (conduction) across the
PCB so it can be dissipated into the air (convection) with minimal heat rise.
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bq24295EVM-549 (PWR549) User’s Guide
SLUUAO5B – August 2013 – Revised April 2014
Copyright © 2013–2014, Texas Instruments Incorporated
