FB
LM34917A
V
OUT
RON/SD
VIN
C1
SS
RTN
GND
3B
2A
On
Timer
Minimum
Off Timer
Logic
IN
Regulation
Comparator
Current Limit
Detect
8V to 33V
1.0
P
F
2C
C3
R1
22.1k
0.1
P
F
2B
1C
3A
C6
0.022
P
F
V
IN
10
P
F
SW
ISEN
SGND
5V
1D
3D
0.047
P
F
C4
0.1
P
F
L1
15
P
H
R6 0
:
2D
1B
D1
1A
R2
2.49k
R3
2.49k
R4
0.27
:
C7
C8
+
-
VCC
3C
BST
C5
2.5V
Cff
10
P
F
C2
GND
1.0
P
F
470 pF
Cff =
t
ON (max)
(R2//R3)
Output Ripple Control
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B) Intermediate Ripple Level Configuration: This configuration generates more ripple at V
OUT
than the
option A configuration, but uses one less capacitor. If some ripple can be tolerated in the application, this
configuration is slightly more economical, and simpler. R5, C9 and C10 are removed. R4 and Cff are
added as shown in
Figure 3
.
R4 is chosen to generate 25-30 mVp-p at V
OUT
knowing that the minimum ripple current is 105 mAp-p at
minimum V
IN
. Cff couples that ripple to the FB pin without the attenuation of the feedback resistors. Cff’s
minimum value is calculated from:
(5)
where t
ON(max)
is the maximum on-time (at minimum V
IN
), and R2//R3 is the equivalent parallel value of the
feedback resistors. For this evaluation board t
ON(max)
is approximately 510 ns, and R2//R3 = 1.25 k
Ω
, and
Cff calculates to a minimum of 408 pF. In the circuit of
Figure 3
the ripple at V
OUT
ranges from
≊
32 mVp-p
to
≊
84 mVp-p over the input voltage range.
Figure 3. Intermediate Ripple Configuration Using Cff and R4
4
AN-1601 LM34917A Evaluation Board
SNOA484D – June 2007 – Revised April 2013
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