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Features of the Evaluation Board
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Features of the Evaluation Board
Seamless design solution, incorporating DP83848 PHYTER® single port 10/100 Mb/s Ethernet physical
layer transceiver and LM5072 High Power PoE PD and PWM controller.
Ethernet
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Integrated or External magnetics and RJ45
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Minimum configuration requirements:
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2 PHY Addresses - 01h (default) or 03h
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Status LEDs – board power, others dependant on LED mode selected
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Limited Strap Options – MDIX_EN, LED_CFG, PWR_DWN/INT, MII/RMII Sel
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RESET_N jumper
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PWR_DWN/INT jumper
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Connections for the following interfaces:
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MIl/RMII Interface (IEEE 802.3 standard)
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RJ-45 Cat-V Ethernet cable connector
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JTAG header
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25MHz_OUT header
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Header for “ribbon cable” connection to MII/RMII
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On-board clock – Crystal/Oscillator Dual Footprint
Power Over Ethernet
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Isolated output voltage: 3.3V
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Maximum output current: 7.3A
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Maximum output power: 24W
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Input voltage ranges:
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PoE input voltage range: 39 to 57V
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AUX input voltage range: 22 to 57V
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Measured maximum efficiency:
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DC to DC converter efficiency: 90% at 6A
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Overall efficiency (including the input diode bridge): 86% at 6A
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Overall Board Size: 5.50” x 3.96” x 0.70”
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Switching frequency: 250 kHz
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Optional input common-mode filter
PCB Layout Considerations
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FR4 material
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Trace symmetry within differential pair (±0.5")
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Differential impedance 100 ohms, ±5%
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Adjacent differential pairs spacing > 2X distance within a differential pair, to minimize cross-talk and
EMI
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Trace length matching between differential pairs not required
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Uniform supply & ground plane
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Void planes under magnetics, except for Chassis GND (at RJ-45 edge only)
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Combination of through-hole and surface mount technology
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Trace/space will be 0.007”/0.008” minimum
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System interface will be via the MII connector, and MII header
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RJ-45 for network connection
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JTAG access via 2x5 header
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AN-1521 POEPHYTEREV-I / -E Evaluation Board
SNOA476C – October 2006 – Revised April 2013
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