Factors Limiting the Minimum Operating Input Voltage
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A unique characteristic of the flyback topology is its power transformer. Unlike an ordinary power
transformer that simultaneously transfers the power from the primary to the secondary, the flyback
transformer first stores the energy inside the transformer while the main switch is turned on, and then
releases the stored energy to the load during the rest of the cycle. When the stored energy is not
completely released before the main switch is turned on again, it is said that the flyback converter
operates in continuous conduction mode (CCM). Otherwise, it is in discontinuous conduction mode
(DCM).
Major advantages of CCM over DCM include (i) lower ripple current and ripple voltage, resulting in smaller
input and output filter capacitors; and (ii) lower RMS current, thus reducing the conduction losses. To keep
the flyback converter in CCM at light load, the transformer’s primary inductance should be designed as
large as is practical.
Major drawbacks of CCM, as compared to DCM, are (i) the presence of the right-half-plane zero, which
may limit the achievable bandwidth of the feedback loop, and (ii) the need for slope compensation to
stabilize the feedback loop at duty cycles greater than 50%.
The flyback topology can have multiple secondary windings for several isolated outputs. One or more of
these secondary channels are normally utilized internally by the converter itself to provide the necessary
bias voltages for the controller. The transformer uses an EFD20 type core with a primary inductance of 45
µH. The converter runs in CCM at full load over the entire input voltage range, but it will operate in DCM
under light loads. The LM5072’s built-in slope compensation helps stabilize the feedback loop when the
duty cycle exceeds 50% in 24V AUX power operation.
A additional transformer winding is used to provide the bias voltage (VCC) to the LM5072 IC. Although the
LM5072 controller includes an internal startup regulator which can support the bias requirement
indefinitely, the transformer winding produces an output about 2V higher than the startup regulator output,
thus shutting off the startup regulator and reducing the power dissipation inside the IC. Given the low
current limit value (15 mA nominal) of the high voltage startup regulator, the VCC line is not meant to
source external loads greater than 3 mA in total. The external load of the VCC line is the “PoE Power”
LED indicating the PoE operation mode.
21
Factors Limiting the Minimum Operating Input Voltage
The LM5072 supports operation with as low as 9V AUX power source. However, limited by the flyback
power transformer design, the minimum AUX voltage of the evaluation board is 22V (voltage drops
caused by RE1A and alike and DE1 reduce the VIN pin potential to about 20V).
The installed EFD20 type power transformer FA2267-AL is a low cost, area efficient solution to operate
with a wide auxiliary input voltage range from 24V to 57V. However, it does not support 24W power
operation with the lower input voltage. Under these conditions the excessive magnetic flux may saturate
the transformer core. It is possible to operate with a lower voltage AUX source, if the output power level is
reduced. If full power is required under low AUX input voltage, the power transformer will need to be
redesigned.
22
PoE Performance Characteristics
22.1 PoE Input Power-up Sequence
The PoE power up sequence is as follows. Note that the RTN pin (IC pin 8) is isolated from the +3.3V
RTN output pin of the evaluation board:
1. The circuit first enters detection mode.
2. Depending on the PSE in use, the circuit may or may not go through classification mode.
3. The PSE enters full power application mode. Before the PoE input voltage reaches the UVLO
threshold, the hot swap MOSFET is in the OFF state. Thus, all nodes in the non-isolated section of the
power supply remain at high potential. The voltage across the hot swap MOSFET, namely the voltage
across the RTN and VEE pins, will be approximately equal to the PoE input voltage seen across the
VIN and VEE pins.
4. When the UVLO is released during the PoE input power up, the drain of the internal hot swap
MOSFET is pulled down to VEE (IC pin 7) gradually as the input current charges up the input
capacitors.
10
AN-1521 POEPHYTEREV-I / -E Evaluation Board
SNOA476C – October 2006 – Revised April 2013
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