Software Control
FIFO pointer offset and various FIFO alarms.
•
Clock Settings.
This section allows the user to specify which clock mode is desired as well as trim the
clock RC filter. Ensuring that the other AFE7070 settings and CDCM7005 settings are consistent with
the choice of clock mode is important. For reference, the following is a summary of the relevant
settings for each mode:
–
Dual Input Clock –
Configure CLKIO on the CDCM7005 tab to be an active CMOS signal at either
1x or 2x the desired sampling rate. Set DACCLK to active, LVPECL levels, and 2x the desired
sampling rate. Set the data type in the AFE7070 tab’s
Digital Input Settings
section to either IQ or
Phase data. Configure the FIFO as desired. Connect the CDC OUT output via the SMA to the
TSW1400, and configure as an active CMOS output at the same frequency as DACCLK.
–
Dual Output Clock –
In this mode, CLKIO is an output and must not be connected to the
CDCM7005 (see
for the necessary hardware modifications). DACCLK must be an
active LVPECL clock at 2x the desired sampling rate. Set the data type in the AFE7070 tab’s
Digital
Input Settings
section to either IQ or Phase data. In this mode, the FIFO is disabled automatically.
–
Single Differential DDR Clock –
CLKIO is not used in this mode, so it can be disabled in the
CDCM7005 settings. An LVPECL-level DACCLK must be provided at 1x the desired sampling rate.
Either IQ or Phase data is allowed, and the FIFO is disabled automatically. Connect the CDC OUT
output to the TSW1400 by way of the SMA, and configure it as an active CMOS output at 2x the
DACCLK frequency.
–
Single Differential SDR Clock –
CLKIO is unused and can be disabled. Provide an LVPECL-level
DACCLK at 1x the desired sampling rate. Only use this mode for Phase data. Connect the CDC
OUT output to the TSW1400 by way of the SMA, and configure it as an active CMOS output at 1x
the DACCLK frequency.
•
Mixer/NCO Settings.
Use these controls to enable or disable the AFE7070’s mixer stage as well as
adjust its frequency and initial phase. Note that the frequency values input must be the actual desired
NCO frequency in MHz, not the value to be stored in the frequency registers. The AFE7071 does not
have this function.
•
Digital Input Settings.
These controls affect the way the AFE7070 interprets its input data.
•
Misc. Digital Signals
. These controls affect the way the AFE7070 interprets other digital data. Note
that the GUI generates SPI commands based on a 3-wire serial interface (SIF).
•
QMC Settings.
These controls allow the user to adjust QMC offset (to reduce carrier feedthrough) and
gain/phase (to improve sideband suppression).
•
LVDS Clock Divider.
This section sets the divide ratio for the LVDS output. Note that this output’s
frequency can range from 100 MHz to 800 MHz.
•
Analog Output Settings.
These controls affect the internal DAC outputs. The full-scale current setting
is 15. The
Trim Analog Filters
slider can adjust the corner frequency of the baseband low-pass filter.
The maximum filter corner is 10 MHz.
•
Atest.
These controls activate various test modes and are not useful to most users.
2.2.2
CDCM7005 Controls
The CDCM7005 tab provides full programming control of the CDCM7005 device.
displays a
screen shot of this tab. . Not all of the functions may be of interest in evaluating AFE7070 performance.
The tab is divided into three sections:
•
Advanced Options.
These settings provide advanced control of the CDCM7005 device. Their
functions are beyond the scope of this document. For a detailed description of these settings, consult
the CDCM7005 data sheet (
).
•
Clock & PLL Options.
This section is only enabled when the CDCM7005 is in PLL mode and allows
the user to specify (manually or automatically) the necessary M and N divider settings to produce a
desired VCXO frequency output.
•
Output Options.
These controls allow configuration for various CDCM7005 outputs. The only outputs
of interest are Y1 (the AFE7070’s CLK_IO), Y3 (the AFE7070’s DACCLK), and Y4 (CDC OUT, which
can be used to provide a clock to the TSW1400). The user can specify the output levels (LVPECL or
LVCMOS), a divide ratio, and whether or not each signal is active or high-impedance.
6
AFE707xEVM Evaluation Module
SLOU337A – March 2012 – Revised July 2015
Copyright © 2012–2015, Texas Instruments Incorporated
