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Typical AFE5801 Bench Setup:
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Clock Selection Jumper Configurations: (a) Transformer (default); (b) Single-ended Clock; (c) Future
CLK Input Option Based on U1. Both (b) and (c) Configurations Need Some Modifications on the PCB.
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Schematic Page 1
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Schematic Page 2
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Schematic Page 3
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Schematic Page 4
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Schematic Page 5
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Schematic Page 6
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Top Layer Signal
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Inner Layer 1 Ground
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Inner Layer 2 Signal
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Inner Layer 3 Power
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Inner Layer 4 Ground
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Bottom Layer Signal
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Top Silk Screen Layer
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Bottom Silk Screen Layer
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Typical Performance of AFE5801. (a) Fixed Gain Mode; (b) Variable Gain Mode
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Connection Between TSW1250EVM and AFE5801
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Connection of the Instruments
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AFE5801EVM GUI - RUN Mode
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AFE5801 EVM GUI - START Button
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AFE5801EVM GUI - Variable Gain
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AFE5801EVM GUI - Setting Fixed Gain
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User Interface: Initial Setup Screen
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User Interface: Step-by-Step Setup
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User Interface: Frequency Load Value to Signal Generator
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User Interface: Final Setup Screen
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User Interface: Single FFT Format
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User Interface: Time Domain Format
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Plot of Saved Sample Data
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TSW1100 Interface
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Analysis of Non-Coherent Sampled Data. (a) No window applied; (b) Hanning window applied.
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List of Tables
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Channel-to-Channel Matching Between the AFE5801EVM and ADSDeSER-50EVM
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AFE5801 8-Channel Variable Gain Amplifier (VGA) with Octal High-Speed ADC
SLOU257A
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October 2009
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Revised July 2011
Copyright
©
2009
–
2011, Texas Instruments Incorporated