EVM Digital Interface
4
EVM Digital Interface
Samtec part numbers SSW-110-22-F-D-VS-K and TSM-110-01-L-DV-P provide a convenient 10-pin, dual-
row, header and socket combinations at P1. The header and socket provide access to the ADC digital
control pins. Consult Samtec at
or call 1-800-SAMTEC-9 for a variety of mating
connector options.
summarizes the pinouts for digital interface J2.
Table 3. J2: Serial Interface Header
Pin Number
Signal
Description
Chip-select input that can be used as a convert
J2.1
CS or CONVST
start
J2.3
SCLK
Serial clock input
Chip-select input that can be used as a convert
J2.7
CS or CONVST
start meant for the MMB0 motherboard
J2:13
SDO or MISO
SDO or MISO output
20-k
Ω
pull-up resistor for detecting falling edges at
J2.15
INT
the end of conversion
Direct connection to the convert start pin if JP3 is
J2.17
CONVST
installed
J2.4, J2.10, and J2.18
GND
Digital ground connections
I
2
C bus; used only to program the U4 EEPROM on
J2.16, J2.20
I
2
C™ bus
the EVM board
J2.2, J2.5-6, J2.8-9,
J2.11-12, J2.14, and
Unused
Unused
J2:19
4.1
Serial Interface (SPI)
The ADS8860 ADC uses SPI serial communication in mode 1 (CPOL = 0, CPHA = 1) with high-speed
clocks higher than 30 MHz; for slower clocks, mode 0 is used (CPOL = 0, CPHA = 0). Because the serial
clock (SCLK) frequency can be as fast as 80 MHz, the ADS8860EVM offers 47-
Ω
resistors between the
SPI signals and J2 to aid with signal integrity. Typically, in high-speed SPI communication, fast signal
edges can cause overshoot; these 47-
Ω
resistors slow down the signal edges in order to minimize signal
overshoot.
4.2
I
2
C Bus for Onboard EEPROM
The ADS8860EVM has an I
2
C bus that records the board name and assembly date to communicate with
the onboard EEPROM. The bus is not used in any form by the ADS8860 converter.
6
ADS8860EVM-PDK
SBAU213 – September 2013
Copyright © 2013, Texas Instruments Incorporated