Texas Instruments ADS8860EVM-PDK, Руководство пользователя, Страница: 5 / 20

5V
5V
0.22
+
-
+
1k
1µF
+
-
+
OPA333
THS4281
10µF
1µF
20k
1k
1µF
Vref
4.5V from
REF5045
AINP
AINN
10000pF
4.7
4.7
+
-
1k
OPA836
+2.25V
0.1V
+4.4V
1k
2.25V
5V
A0(-)
JP4 (OPEN)
Transfer Function:
AINP = 4.5V
±
A0(-)
0.1V
4.4V
2.25V
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EVM Analog Interface
3.2 Bipolar Input Signal Configuration
With JP4 open, the OPA836 positive input is biased with +2.25 V, created by diving the 4.5-V onboard
reference by two. This bias becomes a 4.5-V offset at the output of the OPA836 that allows input signals
with a 2.25-V common mode. To keep the OPA836 distortion as low as possible, the input signal swing is
limited from +0.1 V to +4.4 V, as shown in
Figure 2 .
Figure 2. Single-Ended Signal Example
3.3 Voltage Reference
Because the EVM is powered by a 5-V analog supply, the reference should be a value below 5 V. This
EVM uses 4.5 V, created by the onboard REF5045, as shown in
Figure 3 . Then, the EVM is filtered by an
RC filter with a 160-Hz cutoff frequency to minimize noise contribution. Finally, the EVM is buffered by the
THS4281, which can drive the 10
μ F required at the ADC reference (with a 2-MHz effective bandwidth
and 22-
μ
Vrms total noise). The OPA333 and the additional feedback is optional, but does complement the
THS4281, minimizing offset and drift.
Figure 3. THS4281 Reference Driver with Complementary OPA333 for Drift and Offset Correction
5 SBAU213 – September 2013 ADS8860EVM-PDK
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