shows the LDOs used to generate the AVDD, HVDD, and HVSS supplies.
0
R16
0
R8
25V
22uF
C8
100k
R3
1µF
25V
C10
25V
10uF
C9
0
R17
DNP
0
R15
DNP
0
R10
0
R9
DNP
+15 V
TP2
+15 V
0
R2
0
R1
OUT
1
NC
2
SENSE
3
6P4V2
4
6P4V1
5
3P2V
6
GND
7
1P6V
8
0P8V
9
0P4V
10
0P2V
11
0P1V
12
EN
13
NR
14
IN
15
IN
16
NC
17
NC
18
NC
19
OUT
20
PAD
21
TPS7A47 00RGWR
U1
GND
D1
SMAJ15 A
GND
D2
SMAJ15 A
GND
10µ F
C20
10µ F
C26
Gree n
1
2
D4
APT 2012LZ GCK
HVSS
HVDD
GND
GND
HVSS
HVDD
AVDD
Gree n
1
2
D5
APT 2012LZ GCK
GND
6.65 k
R20
AVDD
Gree n
1
2
D3
APT 2012LZ GCK
OUT
1
FB
2
NC
3
GND
4
EN
5
NR/SS
6
DNC
7
IN
8
PAD
9
TPS7A30 01DRBR
U4
-15V
GND
10.0 k
R7
50V
10nF
C17
50V
10nF
C19
GND
25V
10uF
C16
GND
TP3
-15V
25V
10uF
C18
GND
0
R5
0
R4
GND
GND
GND
GND
0
R27
0
R26
DNP
HVDD
HVSS
-15V
+15 V
1
2
3
J1
0
R40
DNP
0
R36
25V
22uF
C29
100k
R29
1µF
25V
C36
25V
10uF
C30
0
R45
DNP
0
R39
0
R38
DNP
0
R37
DNP
0
R28
0
R25
OUT
1
NC
2
SENSE
3
6P4V2
4
6P4V1
5
3P2V
6
GND
7
1P6V
8
0P8V
9
0P4V
10
0P2V
11
0P1V
12
EN
13
NR
14
IN
15
IN
16
NC
17
NC
18
NC
19
OUT
20
PAD
21
TPS7A47 00RGWR
U5
GND
GND
GND
GND
AVDD
BVDD
Gree n
1
2
D6
APT 2012LZ GCK
GND
6.65 k
R30
BVDD
93.1 k
R6
TP21
GND
GND
TP22
GND
GND
TP23
GND
GND
+15 V
10.0 k
R18
10.0 k
R19
Figure 7-3. LDO Schematic
Bill of Materials, Layout, and Schematics
24
ADS8555EVM-PDK Evaluation Module
SLAU298A – NOVEMBER 2009 – REVISED MAY 2021
Copyright © 2021 Texas Instruments Incorporated