Texas Instruments ADS62PXXEVM, Руководство пользователя

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Circuit Description
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Alternatively, the clock may be supplied by an onboard VCXO and CDCE72010 clock buffer. The
CDCE72010 Clock Buffer has been factory programmed to output a clock to the ADC that is 1/4 the rate
of the on-board VCXO. While using this clock option, a separate 20MHz reference clock must be supplied
to the CDCE72010 by way of the Clock Input SMA connector J19 (Surface jumper SJP4 should be
shorted to position 2-3 for this case). The user may also custom program the CDCE72010 with an external
SPI bus by accessing the J22 connector. From the CDCE72010 two clocking options to the ADC are
possible. A differential LVPECL clock output may be connected to the ADC clock input or a single-ended
CMOS clock from the CDCE72010 may be routed to the ADC transformer-coupled clock input through an
on-board crystal filter. For better performance, selecting the CMOS clock through a crystal output is
recommended. Prior to making any jumper settings, see the schematic in the design package.
Table 6
displays the various clock option settings. The VCXO and crystal filter do not come populated on the EVM
by default, although the CDCE72010 Clock buffer is installed.
Table 6. Clock Input Jumper Description
EVM Jumper Description Jumper Setting
1-2 → VCXO enabled
J18 ENABLE VCXO
2-3 → VCXO disabled
J19 Clock Input
1-2
→
powered down
J14 CDCE72010 power down
Open → powered on
1-2 → Reset
J15 CDCE72010 Reset
Open → Normal operation
SJP4 Input Clock Options See Table 7
SJP7 Input Clock Options See Table 7
SJP6 Input Clock Options See Table 7
1-2
→
High (Default)
JP21 Mode select for CDCE72010
2-3 → Low
1-2 → Connects to D3 LED
SJP8 PLLLOCK LED
2-3 → Connects to 10nF capacitor
1-2 → High
JP20 AUX Select pin for CDCE72010
2-3 → Low
J22 SPI Bus Access for CDCE72010 see schematic
12 ADS62PXXEVM SLAU237B – May 2008 – Revised July 2010
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