Alternate Hardware Configurations
15
SLAU687 – May 2016
Copyright © 2016, Texas Instruments Incorporated
ADS54J20EVM
To turn off the ADC clock provided by the LMK04828 to reduce switching noise, click on the
LMK04828
tab, then click on
Clock Outputs
tab, then select
Powerdown
for
DCLK Type
under
CLKout 2 and 3
, as
shown in
.
Figure 9. LMK04828 Clock Outputs Tab
5.1.2
External LMK04828 Clock (Clock Distribution Mode)
The LMK04828 can be used as a clock distributor. In this case, the LMK04828 uses in input clock source
from CLKIN SMA connector (J6). SJP2 (XO_PWR) can be left open to turn off the onboard VCXO to avoid
crosstalk. To use this mode, load the configuration file named
LMK_Config_External_Clock.cfg
. This mode
allows generation of frequencies that are not possible with the LMK when using the on-board VCXO.
5.1.3
Clock Generator Using Onboard VCXO
The LMK04828 is used as a clock generator using the onboard 122.88 MHz VCXO. SJP2 must be shorted
to turn on the onboard VCXO. The internal PLLs of the LMK04828 can be used with the onboard VCXO to
generate the desired frequencies. To use this mode, load one of the configuration files named
LMK_Config_Onboard_xxxx_MSPS.cfg
, where
xxxx
corresponds to the desired ADC sampling rate. A
10-MHz signal can be brought into the CLKIN input to synchronize to external instruments. This is the
board default mode of operation.
5.2
Analog Input Options
The ADS54J20EVM allows for a differential analog input configuration in addition to the default using the
single-ended transformer-coupled input. This option is described in the following section.
5.2.1
Differential Input
The analog input transformers can be bypassed in favor of a differential input source. This allows for a
wider range of input frequencies, including the possibility of DC coupling. To configure the EVM for a
differential analog input on Channel A, remove C6, C7, and R7 and install R3, R4, C1, and C3. For
channel B, remove R8, C14, and C15 and install R21, R22, C12, and C13. For a DC-coupled application,
swap the series capacitors with 0-
Ω
resistors. The input signal must be biased to the required ADC input
common mode voltage.
