Texas Instruments ADS4449 EVM, Руководство пользователя

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J10 CLK IN
1:4
0.1 P F
0.1 P F
121 :
121
:
0.1
P
F
14-bit
ADC
Jp
Jn
0 :
0 :
0 :
0 :
0 :
0 :
0 :
0 :
DNI DNI
D
N
I
D
N
I
D
N
I
25
:
25
:
0.1
P
F 0.1
P
F 0.1
P
F 0.1
P
F
0 :
10 :
10 :
25 :
25
:
82 nH
10 pF
3
rd
Order Bandpass Filter RLR Circuit RLCR Circuit
1:1 1:1
V
CM
Introduction
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6 SLAU485A – January 2013 – Revised April 2016
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ADS4449 EVM User Guide
Table 5. ADS4449 EVM LED Indicators (continued)
Reference
Designator
Description
D2 When lit, D2 shows the presence of the USB to serial converter power
D3 N/A
D4 N/A
1.4 EVM ADC Input Circuit Configurations
Figure 4 shows the ADS4449 ADC input circuit. The default setup has a dual 1:1 impedance ratio
transformer input circuit, which achieves better phase and amplitude balance of the input signal than is
typically produced by a single transformer input circuit. Third-order bandpass filter component pads are
available for installing bandpass filter components. The default components for the bandpass filter are
either zero
Ω
or open circuit.
The default input termination is 50 Ω , which is formed by two 25- Ω resistors connected to the ADC VCM
node. If the user chooses to use 100- Ω termination with the 1:2 impedance transformer, the optional RLR
differential arm can be used to tune the in-band flatness.
The ADC analog input consists of a switched-capacitor-based, differential sample-and-hold (S/H)
architecture. Due to the opening and closing of the sampling glitches, the kick-back noise from the S/H
circuit may affect the ADC performance. Besides the on-chip R-C filter of the ADC input, the external
RLCR circuit provides additional filtering of the glitches. The default RLCR components have been
optimized for input bandwidth centered at 185 MHz.
Figure 4. ADS4449 ADC Input Circuit
Figure 5 shows the ADS4449 clock input circuit. The clock signal goes through the 1:4 impedance ratio
transformer increasing the clock amplitude by two (1:4 impedance ratio equals to 1:2 voltage ratio). The
two 121-
Ω resistors will impedance transform back to the primary side as 50- Ω load impedance for the
signal source generator. For ADC evaluation, set the signal generator output to 10 dBm.
Figure 5. ADS4449 Clock Input Circuit
2 Software Control
2.1 Installation Instructions
• Open the ADS4449_Installer_vxpx folder (xpx represents the latest version, which is 2.0 at the time of