Texas Instruments ADS42JBx9 Скачать руководство пользователя страница 8 | Manualshive

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Texas Instruments ADS42JBx9 Скачать руководство пользователя страница 8

Software Control

www.ti.com

2.2.4

JESD204B Controls

Clicking on either JESD204B Digital block opens the JESD204B Controls window, shown in

Figure 5

. Use

the ADS42JBx9 data sheet for reference to assist with the descriptions of these various controls.

Figure 5. JESD204B Controls Window of the ADS42JBx9 GUI

8

ADS42JBx9 System Evaluation Kit

SLAU468A – November 2012

Submit Documentation Feedback

Copyright © 2012, Texas Instruments Incorporated

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Содержание ADS42JBx9

Страница 1: ...e found in the design package under the ADS42JBx9SEK product folder on www ti com Contents 1 Introduction 2 1 1 Overview 2 1 2 Block Diagram 2 2 Software Control 3 2 1 Installation Instructions 3 2 2...

Страница 2: ...e JESD204B subclass 1 clocking solution The ADS42JB69 and LMK04828 are controlled through an easy to use software GUI enabling quick configuration for a variety of uses The JESD204B translation card c...

Страница 3: ...pin SW3 CPLD Switch inputs to CPLD Currently not used SW2 Reset CPLD CPLD reset SJP12 ADC CNTRL1 pin Not used by ADC Connected to GND JP3 ADC CNTRL2 pin Not used by ADC Connected to GND JP6 XO_PWR Pro...

Страница 4: ...evel view of the GUI which contains the block diagram of the ADS42JBx9 Clicking the blue blocks in the diagram brings up the controls for that block Along the top of the GUI are SEND READ SAVE and LOA...

Страница 5: ...www ti com Software Control Figure 2 Top Level Block Diagram Windor47 4 30436 7 e 0 Td Ton49en4 10 e 0 Blor47 4 3of0 Td...

Страница 6: ...Software Control www ti com 2 2 2...

Страница 7: ...annel A Ch B Gain Enable Enable or disable the gain feature of channel B Ch B Gain Set the gain of channel B Test Pattern A Selects a known test pattern a custom test pattern or normal operation for c...

Страница 8: ...ols window shown in Figure 5 Use the ADS42JBx9 data sheet for reference to assist with the descriptions of these various controls Figure 5 JESD204B Controls Window of the ADS42JBx9 GUI 8 ADS42JBx9 Sys...

Страница 9: ...tal Delay Analog Delay Controls The default lower panel is for output control This is the block called Divider Digital Delay Analog Delay in the block diagram In this panel the desired parameters are...

Страница 10: ...Software Control www ti com...

Страница 11: ...ese values are properly entered and PLL1 becomes locked LED D1 LMK Locked on the ADS42JBx9EVM illuminates Some reasons for this not illuminating are using the wrong divider values or the reference osc...

Страница 12: ...clock design tools when determining external PLL loop filter components Go to the LMK04828 product folder on the TI website to download this tool and other application notes Figure 9 LMK04828 PLL2 Con...

Страница 13: ...in Figure 10 This panel controls the SYSREF output global settings of the LMK04828 The settings made in this panel apply to all SYSREF outputs Figure 10 LMK04828 SYSREF Settings 13 SLAU468A November...

Страница 14: ...core can be found at www xilinx com Table 4 Input and Output Connectors Jumpers and Switches Description of the JESD204B Translation Card Component Description J4 JESD204B FMC connector Interfaces to...

Страница 15: ...VS pin voltage to either 3 3 V or GND Default is 3 3 V SJP8 SJP11 Power monitor program pin interface Selects either J14 or USB Default is J14 3 Basic Test Setup This section outlines basic testing of...

Страница 16: ...Basic Test Setup www ti com Figure 11 Test Setup 16 ADS42JBx9 System Evaluation Kit SLAU468A November 2012 Submit Documentation Feedback Copyright 2012 Texas Instruments Incorporated...

Страница 17: ...ser s Guide SLWU079 for a more detailed explanation of the TSW1400 setup and its features This document assumes that the HSDCPro software and the TSW1400 pattern capture and generation board are both...

Страница 18: ...f SYSREF click on the LMK04828 Outputs tab then click on the SYSREF button In the lower panel go to the MUX panel and set this to SYSREF PULSES This will turn off all of the SYSREF outputs of the LMK...

Страница 19: ...5 Select Single Tone from the Test Selection drop down menu 6 At the bottom left corner enter 250M in the ADC Sampling Rate Fs box If using a coherent frequency input select Auto Calculation of Cohere...

Страница 20: ...ncy energy and has not been tested for compliance with the limits of computing devices pursuant to part 15 of FCC or ICES 003 rules which are designed to provide reasonable protection against radio fr...

Страница 21: ...ompliance could void the user s authority to operate the equipment Concerning EVMs including radio transmitters This device complies with Industry Canada licence exempt RSS standard s Operation is sub...

Страница 22: ...roduct only after you obtained the license of Test Radio Station as provided in Radio Law of Japan with respect to this product or 3 Use of this product only after you obtained the Technical Regulatio...

Страница 23: ...minimize the risk of electrical shock hazard 3 You will employ reasonable safeguards to ensure that your use of the EVM will not result in any property damage injury or death even if the EVM should fa...

Страница 24: ...sponsible for compliance with all legal regulatory and safety related requirements concerning its products and any use of TI components in its applications notwithstanding any applications related inf...

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