Board-Level Control
2-3
Digital Interface
2.1.3
Resetting the ADS1625 and ADS1626
The ADS1625 and ADS1626 are synchronously reset on the EVM when the
RESET pin is asserted LOW. This can be accomplished by issuing a write
command (WR) via the host system or momentarily depressing switch SW2.
Whichever option is chosen, the reset signal is then synchronized with the
modulator clock and is available for application to the RESET pin of the device.
Alternatively, the user can apply the RESET signal directly via W9.
2.1.4
Out of Range Indication
LED D1 indicates if an out of range (OTR) event has occurred. This LED does
not affect the device’s performance. To clear the LED, the device has to be
reset either manually or via SW2.
2.1.5
Interrupt Source
Some microprocessors only recognize falling edge interrupts; others only
recognize rising edge interrupts whereas others may be programmed to
recognize either. By using W11, the user can choose either rising edge
interrupts or falling edge interrupts.
2.1.6
Base Address
The EVM can be mapped into a memory location by setting one of four
possible base addresses. The base address is set by J8. When the logic state
of the two external address signals matches the logic state setup by the two
jumpers on J8 and the access is a valid memory access, the EVM generates
a CS signal for the ADC. This can then be further qualified as a read cycle or
a write (RESET) cycle.
2.1.7
Base Address and Chip Select
An installed jumper is equivalent to logic 0 on the corresponding address line.
An uninstalled jumper is equivalent to logic 1 on the corresponding address
line.
The TMS320C6711 DSK provides two memory spaces for daughter boards.
The two memory-space enables (CE2 and CE3) are buffered versions of the
DSP outputs and are not generated by decode logic on the DSK. The 5−6K
EVM uses CE2 to indicate that the access is valid. This places the daughter
card at an address space beginning at A0000000.
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